1.7. Test features

The Cortex-R7 MPCore processor is delivered as fully-synthesizable RTL and is a fully-static design. Scan-chains and test wrappers for production test can be inserted into the design by the synthesis tools during implementation.

Production test of the processor cache and TCM RAMs can be done through the dedicated, pipelined MBIST interface. This interface shares some of the multiplexing present in the processor design, to improve the potential frequency compared to adding multiplexers to the RAM modules.

The TCM RAMs can be read and written directly by the program running on the processor. You can also use the dedicated AXI3 slave interface to access the TCMs. See Accessing RAMs using the AXI3 interface for more information about how to access the RAMs using the AXI3 slave interface.

Copyright © 2012, 2014 ARM. All rights reserved.ARM DDI 0458C