6.1. About the L1 memory system

The processor L1 memory system can be configured during implementation and integration. It consists of:

Note

  • If both caches and TCMs are present, instructions can be accessed from both the instruction cache and the ITCM.

  • Instructions cannot be accessed from the DTCM.

Each TCM and cache can be configured at implementation time to have an error detection and correction scheme to protect the data stored in the memory from errors. The TCMs are protected by ECC. Chapter 7 Fault Detection describes the error detection and correction schemes.

The MPU is unified, and handles accesses to both the instruction and data sides. The MPU is responsible for protection checking, address access permissions, and memory attributes. Some of these functions can be passed to the L2 memory system through the AXI master. See Memory Protection Unit for more information about the MPU.

The L1 memory system includes a local monitor for exclusive accesses. Exclusive load and store instructions can be used, for example, LDREX, STREX, with the appropriate memory monitoring to provide inter-process or inter-processor synchronization and semaphores. See the ARM® Architecture Reference Manual ARMv7-A and ARMv7-R edition for more information.

Copyright © 2012, 2014 ARM. All rights reserved.ARM DDI 0458C
Non-ConfidentialID112814