6.6. Memory types and L1 memory system behavior

The behavior of the L1 memory system depends on the type attribute of the memory that is being accessed:

Table 6.11 summarizes the processor memory types and associated behavior.

Table 6.11. Memory types and associated behavior

Memory typeCacheableMergingRestartableLocal exclusives Locked swaps
NormalShareable-[a]YesYesPartially[b]Yes
Non-shareableYesYesYesYesNo
DeviceShareableNoNoNoNo[c]No[c]
Non-shareableNoNoNoNo[c]Yes
Strongly OrderedShareableNoNoNoNo[c]Yes

[a] Depends on the value of the ACTLR.SMP bit:

1 = Cacheable.

0 = Non-cacheable.

[b] Depends on the value of the ACTLR.SMP bit:

1 = Exclusive accesses handled using only local monitor.

0 = Exclusive accesses handled using both local and global monitor.

[c] Exclusive accesses are handled using both local and global monitor.


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