9.4.2. Distributor register descriptions

This section describes the registers that the distributor provides. Table 9.17 shows the distributor registers.

Registers not described in Table 9.17 are RAZ/WI. This section does not reproduce information about registers already described in the ARM® Generic Interrupt Controller Architecture Specification 1.0.

The ICDIPR and ICDIPTR registers are byte accessible and word accessible. All other registers in Table 9.17 are word accessible. Any other access is unpredictable.

See Private memory region for the offset of this page from PERIPHBASE[31:13].

Table 9.17. Distributor register summary

BaseNameTypeResetWidthDescription
0x000

ICDDCR

RW0x0000000032

Distributor Control Register

0x004ICDICTR

RO

Configuration dependent32

Interrupt Controller Type Register

0x008ICDIIDRRO0x0300043B32

Distributor Implementer Identification Register

0x00C - 0x09C----

Reserved

0x100 - 0x13CICDISERnRW

0x00000000[a]

32

Interrupt Set-Enable Registers

0x180 - 0x1BCICDICERnRW

0x00000000[b]

32

Interrupt Clear-Enable Registers

0x200 - 0x23CICDISPRnRW

0x00000000

32

Interrupt Set-Pending Registers

0x280 - 0x2BCICDICPRnRW

0x00000000

32

Interrupt Clear-Pending Registers

0x300 - 0x33CICDABRnRO0x0000000032

Active Bit registers

0x380 - 0x3FC----

Reserved

0x400 - 0x4FCICDIPRnRW0x0000000032

Interrupt Priority Registers[c]

0x7FC

----

Reserved

0x800 - 0x9FCICDIPTRn

RW[b]

0x0000000

32

Interrupt Processor Targets Registers

0xBFC

----

Reserved

0xC00 - 0xC7CICDICFRnRW

Configuration dependent

32

Interrupt Configuration Registers

0xD00PPI Status-

0x00000000

32

PPI Status Register

0xD04 - 0xD3CSPI StatusRO

0x00000000

32

SPI Status Registers

0xD80 - 0xEFC----Reserved

0xF00

ICDSGIRWO-32

Software Generated Interrupt Register

0xF04 - 0xFCC----Reserved
0xFD0 - 0xFEC

Peripheral Identification [4:0]

RO

Configuration dependent

8

CoreSight Identification Registers

0xFF0 - 0xFFC

Component Identification [3:0]

RO-8

[a] The reset value for the registers that contain the SGI and PPI interrupts is implementation-dependent.

[b] Not configurable. Reset to 1.

[c] Only the top four bits of each 8-bit field of the register are in use.


Distributor Control Register

The ICDDCR characteristics are:

Purpose

Controls whether the distributor responds to external stimulus changes that occur on SPI and PPI signals.

Usage constraints

There are no usage constraints.

Configurations

Available in all configurations.

Attributes

See the register summary in Table 9.17.

Figure 9.16 shows the ICDDCR bit assignments.

Figure 9.16. ICDDCR bit assignments

To view this graphic, your browser must support the SVG format. Either install a browser with native support, or install an appropriate plugin such as Adobe SVG Viewer.


Table 9.18 shows the ICDDCR bit assignments.

Table 9.18. ICDDCR bit assignments

BitsNameFunction
[31:1]ReservedSBZ
[0]Enable

The encoding is:

0

Disables all interrupt control bits in the distributor from changing state because of any external stimulus change that occurs on the corresponding SPI or PPI signals.

1

Enables the distributor to update register locations for interrupts.


Interrupt Controller Type Register

The ICDICTR characteristics are:

Purpose

Provides information about the configuration of the interrupt controller.

Usage constraints

There are no usage constraints.

Configurations

Available in all configurations.

Attributes

See the register summary in Table 9.17.

Figure 9.17 shows the ICDICTR bit assignments.

Figure 9.17. ICDICTR bit assignments

To view this graphic, your browser must support the SVG format. Either install a browser with native support, or install an appropriate plugin such as Adobe SVG Viewer.


Table 9.19 shows the ICDICTR bit assignments.

Table 9.19. ICDICTR bit assignments

BitsNameFunction
[31:11]ReservedSBZ
[10]ReservedRAZ/WI
[9:8]ReservedSBZ
[7:5]Processor number

The encoding is:

0b000

The configuration contains one Cortex-R7 processor.

0b001

The configuration contains two Cortex-R7 processors.

All other values are unused.

[4:0]IT lines number

The encoding is:

0b00000

The distributor provides 32 interrupts[a], no external interrupt lines.

0b00001

The distributor provides 64 interrupts, 32 external interrupt lines.

0b00010

The distributor provides 96 interrupts, 64 external interrupt lines.

0b00011

The distributor provides 128 interrupts, 96 external interrupt lines.

0b00100

The distributor provides 160 interrupts, 128 external interrupt lines.

0b00101

The distributor provides 192 interrupts, 160 external interrupt lines.

0b00110

The distributor provides 224 interrupts, 192 external interrupt lines.

0b00111

The distributor provides 256 interrupts, 224 external interrupt lines.

0b01000

The distributor provides 288 interrupts, 256 external interrupt lines.

0b01001

The distributor provides 320 interrupts, 288 external interrupt lines.

0b01010

The distributor provides 352 interrupts, 320 external interrupt lines.

0b01011

The distributor provides 384 interrupts, 352 external interrupt lines.

0b01100

The distributor provides 416 interrupts, 384 external interrupt lines.

0b01101

The distributor provides 448 interrupts, 416 external interrupt lines.

0b01110

The distributor provides 480 interrupts, 448 external interrupt lines.

0b01111

The distributor provides 512 interrupts, 480 external interrupt lines.

All other values are unused.

[a] The distributor always uses interrupts of IDs 0 to 31 to control any SGIs and PPIs that the interrupt controller might contain.


Interrupt Processor Targets Registers

This section describes the implementation defined features of the ICDIPTRn. For systems that support only one Cortex-R7 processor, all these registers read as zero, and writes are ignored.

Note

If the Processer Target field is set to 0 for a specific SPI, this interrupt cannot be set pending through the hardware pins or a write to the Set-Pending Register.

Interrupt Configuration Registers

This section describes the implementation defined features of the ICDICFR. Each bit-pair describes the interrupt configuration for an interrupt. The options for each pair depend on the interrupt type as follows:

SGI

The bits are read-only and a bit-pair always reads as 0b10.

PPI

The bits are read-only:

PPI[1] and [4]:0b01

Interrupt is active-LOW level sensitive.

PPI[0]:0b01

Interrupt is active-HIGH level sensitive.

PPI[2] and [3]:0b11

Interrupt is rising-edge sensitive.

SPI

The LSB of a bit-pair is read-only and is always 0b1. You can program the MSB of the bit-pair to alter the triggering sensitivity as follows:

0b01

Interrupt is active-HIGH level sensitive.

0b11

Interrupt is rising-edge sensitive.

There are 31 LSPIs, interrupts 32-62.

Distributor Implementer Identification Register

The ICDIIDR characteristics are:

Purpose

Provides information about the implementer and the revision of the controller.

Usage constraints

There are no usage constraints.

Configurations

Available in all configurations.

Attributes

See the register summary in Table 9.17.

Figure 9.18 shows the ICDIIDR bit assignments.

Figure 9.18. ICDIIDR bit assignments

To view this graphic, your browser must support the SVG format. Either install a browser with native support, or install an appropriate plugin such as Adobe SVG Viewer.


Table 9.20 shows the ICDIIDR bit assignments.

Table 9.20. ICDIIDR bit assignments

BitsValuesNameDescription
[31:24]0x03Implementation versionGives implementation version number.
[23:12]0x00Revision numberReturns the revision number of the controller.
[11:0]0x43BImplementerImplementer number.

PPI Status Register

The PPI Status Register characteristics are:

Purpose

Enables a Cortex-R7 processor to access the status of the inputs on the distributor.

Usage constraints

A Cortex-R7 processor can only read the status of its own PPI and therefore cannot read the status of PPI for other Cortex-R7 processors.

Configurations

Available in all configurations.

Attributes

See the register summary in Table 9.17.

Figure 9.19 shows the PPI Status Register bit assignments.

Figure 9.19. PPI Status Register bit assignments

To view this graphic, your browser must support the SVG format. Either install a browser with native support, or install an appropriate plugin such as Adobe SVG Viewer.


Table 9.21 shows the PPI Status Register bit assignments.

Table 9.21. PPI Status Register bit assignments

BitsNameFunction
[31:16]ReservedSBZ
[15:11]

ppi_status

Returns the status of the PPI[4:0] inputs on the distributor:

PPI[4]

nIRQ.

PPI[3]

Private watchdog.

PPI[2]

Private timer.

PPI[1]

nFIQ.

PPI[0]

Global timer.

PPI[1] and PPI[4] are active LOW

PPI[0], PPI[2], and PPI[3] are active HIGH.

Note

These bits return the actual status of the PPI[4:0] signals. The ICDISPRn and ICDICPRn registers can also provide the PPI[4:0] status but because you can write to these registers then they might not contain the actual status of the PPI[4:0] signals.

[10:0]ReservedSBZ

SPI Status Registers

The SPI Status Register characteristics are:

Purpose

Enables a Cortex-R7 processor to access the status of IRQS[N:0] inputs on the distributor.

Usage constraints

There are no usage constraints.

Configurations

Available in all configurations.

Attributes

See the register summary in Table 9.17.

Figure 9.20 shows the SPI Status Register bit assignments.

Figure 9.20. SPI Status Register bit assignments

To view this graphic, your browser must support the SVG format. Either install a browser with native support, or install an appropriate plugin such as Adobe SVG Viewer.


Table 9.22 shows the SPI Status Register bit assignments.

Table 9.22. SPI Status Register bit assignments

BitsNameDescription
[31:0]spi_status

Returns the status of the IRQS[N:0] inputs on the distributor:

Bit[X] = 0

IRQS[X] is LOW.

Bit[X] = 1

IRQS[X] is HIGH.

Note

The IRQS that X refers to depends on its bit position and the base address offset of the SPI Status Register as Figure 9.21 shows.

These bits return the actual status of the IRQS signals. The ICDISPRn and ICDICPRn Registers can also provide the IRQS status but because you can write to these registers then they might not contain the actual status of the IRQS signals.


Figure 9.21 shows the address map that the distributor provides for the SPIs.

Figure 9.21. SPI Status Register address map

To view this graphic, your browser must support the SVG format. Either install a browser with native support, or install an appropriate plugin such as Adobe SVG Viewer.


In Figure 9.21 the values for the SPIs are read-only. This register contains the values for the SPIs for the corresponding Cortex-R7 processor interface. The distributor provides up to seven registers. If you configure the interrupt controller to use fewer than 480 SPIs then it reduces the number of registers accordingly. For locations where interrupts are not implemented, the distributor:

  • Ignores writes to the corresponding bits.

  • Returns 0 when it reads from these bits.

Copyright © 2012, 2014 ARM. All rights reserved.ARM DDI 0458C
Non-ConfidentialID112814