9.4.1. About the interrupt controller

The interrupt controller is a single functional unit that is located in a Cortex-R7 MPCore processor design. There is one interrupt interface per processor in the design. This implementation of the interrupt controller does not support the Security Extensions.

The interrupt controller is memory-mapped. The Cortex-R7 processors access it by using a private interface through the SCU. See Private memory region.

Interrupt controller clock frequency

The interrupt controller runs on PERIPHCLK. The clock period is configured, during integration, as an integer division of the Cortex-R7 MPCore processor clock (CLK) period. This division, N, must be greater than or equal to two. As a consequence, the minimum pulse width of signals driving external interrupt lines is N CLK cycles. See Clocking, resets, and initialization for a description of PERIPHCLK and PERIPHCLKEN.

The timers and watchdogs use the same clock as the interrupt controller.

Interrupt distributor interrupt sources

The interrupt distributor centralizes all interrupt sources before dispatching the highest priority ones to each Cortex-R7 processor.

The Cortex-R7 MPCore processor supports only the 1-N service model.

All interrupt sources are identified by a unique ID. All interrupt sources have their own configurable priority and list of targeted Cortex-R7 processors. This is a list of processors that the interrupt is sent to when triggered by the interrupt distributor.

Interrupt sources are of the following types:

Software Generated Interrupts (SGI)

Each Cortex-R7 processor has private interrupts, ID0-ID15, that can only be triggered by software. These interrupts are aliased so that there is no requirement for a requesting processor to determine its own processor ID when it deals with SGIs. The priority of an SGI depends on the value set by the receiving processor in the banked SGI priority registers, not the priority set by the sending processor.

Global timer, PPI[0]

The global timer uses ID27. See Global timer.

A legacy nFIQ input, PPI[1]

In the Cortex-R7 processor, the nFIQ input is connected both to the corresponding processor and to the GIC. If the interrupt controller is enabled, nFIQ is mapped to PPI[1], and can still cause an IRQ exception.

When a Cortex-R7 processor uses the interrupt controller, rather than the legacy input in the legacy mode, by enabling its own processor interface, the legacy nFIQ input is also treated like other interrupt lines and uses ID28. In this case, you can mask the legacy FIQ interrupt by setting bit[6] of the CPSR, the F bit, so that only the interrupt line of the GIC is used.

Private timer, PPI[2]

Each Cortex-R7 processor has its own private timers that can generate interrupts, using ID29. See Private timer and watchdog.

Watchdog timers, PPI[3]

Each Cortex-R7 processor has its own watchdog timers that can generate interrupts, using ID30. See Private timer and watchdog.

A legacy nIRQ input, PPI[4]

In legacy IRQ mode the legacy nIRQ input, on a per processor basis, bypasses the interrupt distributor logic and directly drives interrupt requests into the Cortex-R7 processor.

When a Cortex-R7 processor uses the interrupt controller, rather than the legacy input in the legacy mode, by enabling its own processor interface, the legacy nIRQ input is treated like other interrupt lines and uses ID31.

Shared Peripheral Interrupts (SPI)

SPIs are triggered by events generated on associated interrupt input lines. The interrupt controller can support up to 480 interrupt input lines. The interrupt input lines can be configured to be edge sensitive (posedge) or level sensitive (high level). SPIs start at ID32. The IRQS bus generates SPIs.

Note

The Cortex-R7 MPCore processor does not provide internal synchronization for the interrupt signals, nIRQ, nFIQ, and IRQS.

Priority formats

The Cortex-R7 MPCore processor implements a four-bit version of the priority format in the ARM® Generic Interrupt Controller Architecture Specification.

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