10.5.2. Debug registers

The following sections describe the debug registers:

Register interfaces

The Cortex-R7 MPCore processor implements Baseline CP14, Extended CP14, and memory-mapped interfaces. You can access the debug registers as follows:

  • Through the cp14 interface. The debug registers are mapped to coprocessor instructions.

  • Through the APB using the relevant offset.

Debug register mapping

Table 10.8 shows the debug register mapping. All other registers are described in the ARM Architecture Reference Manual.

Table 10.8. Debug register mapping

Register number APB offset APB access CP14 address CP14 access Register name Description
00x000RO 0, c0, c0, 0 RO



128No accessNo access0, c1, c0, 0 RO DBGDRARa-
256No accessNo access0, c2, c0, 0 RO


1No accessNo access0, c0, c1, 0 RO


5No accessNo access0, c0, c5, 0 RO


No accessNo accessWODBGDTRTXinta-
6 0x018 RW 0, c0, c6, 0 RW DBGWFAR Use of DBGWFAR is deprecated in the ARMv7 architecture, because watchpoints are synchronous
7 0x01C RW 0, c0, c7, 0 RW DBGVCR -
8 ----Reserved -
9 No accessNo access0, c0, c9, 0 RAZ/WIDBGECR Not implemented
10 No accessNo access0, c0, c10, 0 RAZ/WIDBGDSCCR Not implemented
11 No accessNo access0, c0, c11, 0 RAZ/WIDBGDSMCR Not implemented
12-31 ----Reserved -
32 0x080 RW 0, c0, c0, 2 RW DBGDTRRXext-
33 0x084 WO 0, c0, c1, 2WO DBGITR -
33 0x084RO 0, c0, c1, 2 RO DBGPCSR -
34 0x088RW 0, c0, c2, 2 RW DBGDSCRext-
35 0x08CRW 0, c0, c3, 2 RW DBGDTRTXext-
36 0x090WO 0, c0, c4, 2 WO DBGDRCR -
37-63 ----Reserved -


RW 0, c0, c0-c5, 4RW DBGBVRn Breakpoint Value Registers


RW 0, c0, c0-c5, 5RW DBGBCRn Breakpoint Control Registers


RW 0, c0, c0-c3, 6RW DBGWVRn Watchpoint Value Registers


RW 0, c0, c0-c3, 7 RW DBGWCRn Watchpoint Control Registers
116-191 ----Reserved -
192 0x300RAZ/WI 0, c1, c0, 4 RAZ/WI DBGOSLAR Not implemented
193 0x304RAZ/WI0, c1, c1, 4RAZ/WIDBGOSLSR Not implemented
194 0x308RAZ/WI 0, c1, c2, 4RAZ/WI DBGOSSRRNot implemented
195 ----Reserved -
196 0x310RW 0, c1, c4, 4 RW DBGPRCR -
197 0x314RO 0, c1, c5, 4 RO DBGPRSR -
198-511 ----Reserved -



PMU registers[c]

576-831 ----Reserved -


----Processor ID Registers
896-927 - - Reserved -


RAZ/WINo accessNo access--
9600xF00RAZ/WI0, c7, c0, 4RAZ/WIDBGITCTRLIntegration Mode Control Register


---- -
10000xFA0RW0, c7, c8, 6RWDBGCLAIMSETClaim Tag Set Register
10010xFA4RW0, c7, c9, 6RWDBGCLAIMCLRClaim Tag Clear Register
1004 0xFB0WONo accessNo accessDBGLARLock Access Register
1005 0xFB4RONo accessNo accessDBGLSRLock Status Register
10060xFB8RO0, c7, c14, 6RODBGAUTHSTATUSAuthentication Status Register
10090xFC4RONo accessNo accessDBGDEVID1-
10100xFC8RONo accessNo accessDBGDEVID-
10110xFCCRONo accessNo accessDBGDEVTYPEDevice Type Register


RONo accessNo accessPERIPHERALIDCoreSight Identification Registers


RONo accessNo accessCOMPONENTIDCoreSight Identification Registers

[a] Baseline CP14 interface. This register also has an external view through the memory-mapped interface and the CP14 interface.

[b] Accessible in user mode if bit [12] of the DBGSCR is clear. Also accessible in privileged modes.

[c] PMU registers are part of the CP15 interface. Reads from the extended CP14 interface return zero. See Register summary. See also Performance Monitoring Unit.

Debug register descriptions

This section describes register features specific to the Cortex-R7 MPCore processor. See the ARM Architecture Reference Manual for information about other register features not described in this section.

Debug Status and Control Register, DBGDSCR

Behaves as described in the ARM Architecture Reference Manual, except for the following bits:

PipeAdv, bit[25]

This bit is set each time a branch is resolved in the processor.

HALTED, bit[0]

This bit is the only bit of the register that is not reset on debug logic reset. It is reset to 1'b0 on a processor logic reset. Its behavior is as described in the ARM Architecture Reference Manual.

Debug Run Control Register, DBGDRCR

Behaves as described in the ARM Architecture Reference Manual, except for the following bits:

Cancel BIU Requests, bit[4]

Not implemented, RAZ/WI.


Implemented as described in the ARM Architecture Reference Manual.

Device Powerdown and Reset Control Register, DBGPRCR

Behaves as described in the ARM Architecture Reference Manual, except for the following bits:


Not implemented, RAZ/WI.

DBGnoPWRDWN, bit[0]

Implemented as described in the ARM Architecture Reference Manual (RW).

Device Powerdown and Reset Status Register, DBGPRSR

Behaves as described in the ARM Architecture Reference Manual, except for the following bits:

Sticky Reset Status, bit[3]

Implemented as described in the ARM Architecture Reference Manual.

Reset Status, bit[2]

Implemented as described in the ARM Architecture Reference Manual.

Sticky Powerdown Status, bit[1]

Not implemented, RAZ/WI.

Power-up Status, bit[0]

Implemented, RAO.

Breakpoint and Watchpoint Registers, DBGBVRn, DBGBCRn, DBGWVRn, and DBGWCRn

Behave as described in the ARM Architecture Reference Manual, except for the following:

  • Only BRP4 and BRP5 support context ID comparison.

  • BVR0[1:0], BVR1[1:0], BVR2[1:0], and BVR3[1:0] are SBZP on writes and RAZ on reads because these registers do not support context ID comparisons.

  • The context ID value for a BVR to match with is given by the contents of the CP15 Context ID Register.

Effects of resets on debug registers


nDBGRESET is the debug logic reset signal. This signal must be asserted during a powerup reset sequence.

On a debug reset:

  • The debug state is unchanged. That is, DBGSCR.HALTED is unchanged.

  • The processor removes the pending halting debug events DBGDRCR.HaltReq.

Debug management registers

The management registers define the standardized set of registers that is implemented by all CoreSight components. Table 10.9 shows the contents of the debug management registers for the Cortex-R7 debug unit. On the Cortex-R7 MPCore processor, the debug management registers are memory-mapped.

Table 10.9. Debug management registers

APB offsetRegister numberAccessMnemonicDescription
0xD00-0xDFC832-895RO-Processor ID Registers
0xE00-0xEF0854-956RAZ/WI-Not implemented
0xF04-0xF9C961-999RAZ/WI-Not implemented
0xFA8-0xFBC1002-1003RAZ/WI-Not implemented
0xFBC-0xFC41007-1009RAZ/WI-Not implemented
0xFD0-0xFFC1012-1023RO-CoreSight Identification Registers

Processor ID Registers

The Processor ID Registers are read-only registers that return the same values as the corresponding CP15 ID Code Register and Feature ID Register.

Table 10.10 shows the APB offset value, register number, mnemonic, and description that are associated with each Processor ID Register.

Table 10.10. Processor ID Registers

APB offsetRegister numberMnemonicAccessRegister valueDescription
0xD00832MIDRRO-[a]Main ID Register alias
0xD04833CTRRO0x8333C003Cache Type Register
0xD08834TCMTRRO-[b]TCM Type Register
0xD0C835MIDRRO-[a]Main ID Register alias
0xD10836MPUIRRO-[c]MPU Type Register
0xD14837MPIDRRO-[d]Multiprocessor Affinity Register
0xD18838REVIDRRO0x0Revision ID Register
0xD1C839MIDRRO-[a]Main ID Register alias
0xD20840ID_PFR0RO0x00000131Processor Feature Register 0
0xD24841ID_PFR1RO0x00000001Processor Feature Register 1
0xD28842ID_DFR0RO0x00010404Debug Feature Register 0
0xD2C843ID_AFR0RAZ-Auxiliary Feature Register 0
0xD30844ID_MMFR0RO0x00110130Memory Model Feature Register 0
0xD34845ID_MMFR1RO0x0Memory Model Feature Register 1
0xD38846ID_MMFR2RO0x01200000Memory Model Feature Register 2
0xD3C847ID_MMFR3RO0x00002111Memory Model Feature Register 3
0xD40848ID_ISAR0RO0x02101111Instruction Set Attribute Register 0
0xD44849ID_ISAR1RO0x13112111Instruction Set Attribute Register 1
0xD48850ID_ISAR2RO0x21232141Instruction Set Attribute Register 2
0xD4C851ID_ISAR3RO0x01112131Instruction Set Attribute Register 3
0xD50852ID_ISAR4RO0x00010142Instruction Set Attribute Register 4
0xD54853ID_ISAR5RAZ-Instruction Set Attribute Register 5

[a] 0x41nFC17m:

    n = variant.

    m = revision.

[b] TCM present = 0x80010001.TCM not present = 0x0.

[c] MPU_16 configuration = 0x00001000.

MPU_12 configuration = 0x00000C00.

[d] Dependent on cluster and processor IDs:

With one processor = 0x80000000.

With two processors = 0xC0000n0m.

     n = CLUSTERID input.     m = processor number (0x0 for processor 0, 0x1 for processor 1.

CoreSight Identification Registers

The Identification Registers are read-only registers that consist of the Peripheral Identification Registers and the Component Identification Registers. The Peripheral Identification Registers provide standard information required by all CoreSight components. Only bits[7:0] of each register are used.

The Component Identification Registers identify the processor as a CoreSight component. Only bits[7:0] of each register are used, the remaining bits Read-As-Zero. The values in these registers are fixed.

Table 10.11 shows the APB offset value, register number, and description that are associated with each Peripheral Identification Register.

Table 10.11. Peripheral Identification Registers for processor debug

APB offsetRegister numberValueDescription
0xFD010120x04Peripheral Identification Register 4
0xFE010160x17Peripheral Identification Register 0
0xFE410170xBCPeripheral Identification Register 1
0xFE810180x0BPeripheral Identification Register 2
0xFEC10190x00Peripheral Identification Register 3

Table 10.12 shows the APB offset value, register number, and value that are associated with each Component Identification Register.

Table 10.12. Component Identification Registers

APB offsetRegister numberValueDescription
0xFF010200x0DComponent Identification Register 0
0xFF410210x90Component Identification Register 1
0xFF810220x05Component Identification Register 2
0xFFC10230xB1Component Identification Register 3

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