ARM Cortex-R7 MPCore Technical Reference Manual: 10.5.2. Debug registers

10.5.2. Debug registers

The following sections describe the debug registers:

Register interfaces

The Cortex-R7 MPCore processor implements Baseline CP14, Extended CP14, and memory-mapped interfaces. You can access the debug registers as follows:

Through the cp14 interface. The debug registers are mapped to coprocessor instructions.
Through the APB using the relevant offset.

Debug register mapping

Table 10.8 shows the debug register mapping. All other registers are described in the ARM Architecture Reference Manual.

Table 10.8. Debug register mapping

Register number	APB offset	APB access	CP14 address	CP14 access	Register name	Description
0	`0x000`	RO	`0, c0, c0, 0`	RO	DBGDIDR^[a]	-^[b]
128	No access	No access	`0, c1, c0, 0`	RO	DBGDRAR^a	-
256	No access	No access	`0, c2, c0, 0`	RO	DBGDSAR^a	-
1	No access	No access	`0, c0, c1, 0`	RO	DBGDSCRint^a^b	-
5	No access	No access	`0, c0, c5, 0`	RO	DBGDTRRXint^a	-
5	No access	No access	`0, c0, c5, 0`	WO	DBGDTRTXint^a	-
6	`0x018`	RW	`0, c0, c6, 0`	RW	DBGWFAR	Use of DBGWFAR is deprecated in the ARMv7 architecture, because watchpoints are synchronous
7	`0x01C`	RW	`0, c0, c7, 0`	RW	DBGVCR	-
8	-	-	-	-	Reserved	-
9	No access	No access	`0, c0, c9, 0`	RAZ/WI	DBGECR	Not implemented
10	No access	No access	`0, c0, c10, 0`	RAZ/WI	DBGDSCCR	Not implemented
11	No access	No access	`0, c0, c11, 0`	RAZ/WI	DBGDSMCR	Not implemented
12-31	-	-	-	-	Reserved	-
32	`0x080`	RW	`0, c0, c0, 2`	RW	DBGDTRRXext	-
33	`0x084`	WO	`0, c0, c1, 2`	WO	DBGITR	-
33	`0x084`	RO	`0, c0, c1, 2`	RO	DBGPCSR	-
34	`0x088`	RW	`0, c0, c2, 2`	RW	DBGDSCRext	-
35	`0x08C`	RW	`0, c0, c3, 2`	RW	DBGDTRTXext	-
36	`0x090`	WO	`0, c0, c4, 2`	WO	DBGDRCR	-
37-63	-	-	-	-	Reserved	-
64-69	`0x100`-`0x114`	RW	`0, c0, c0-c5, 4`	RW	DBGBVRn	Breakpoint Value Registers
70-79	-	-	-	-	Reserved	-
80-85	`0x140`-`0x154`	RW	`0, c0, c0-c5, 5`	RW	DBGBCRn	Breakpoint Control Registers
86-95	-	-	-	-	Reserved	-
96-99	`0x180`-`0x18C`	RW	`0, c0, c0-c3, 6`	RW	DBGWVRn	Watchpoint Value Registers
100-111	-	-	-	-	Reserved	-
112-115	`0x1C0`-`0x1CC`	RW	`0, c0, c0-c3, 7`	RW	DBGWCRn	Watchpoint Control Registers
116-191	-	-	-	-	Reserved	-
192	`0x300`	RAZ/WI	`0, c1, c0, 4`	RAZ/WI	DBGOSLAR	Not implemented
193	`0x304`	RAZ/WI	`0, c1, c1, 4`	RAZ/WI	DBGOSLSR	Not implemented
194	`0x308`	RAZ/WI	`0, c1, c2, 4`	RAZ/WI	DBGOSSRR	Not implemented
195	-	-	-	-	Reserved	-
196	`0x310`	RW	`0, c1, c4, 4`	RW	DBGPRCR	-
197	`0x314`	RO	`0, c1, c5, 4`	RO	DBGPRSR	-
198-511	-	-	-	-	Reserved	-
512-575	`0x800`-`0x8FC`	-	-	-	-	PMU registers^[c]
576-831	-	-	-	-	Reserved	-
832-895	`0xD00`-`0xDFC`	-	-	-	-	Processor ID Registers
896-927	-		-		Reserved	-
928-959	`0xE80`-`0xEFC`	RAZ/WI	No access	No access	-	-
960	`0xF00`	RAZ/WI	`0, c7, c0, 4`	RAZ/WI	DBGITCTRL	Integration Mode Control Register
961-999	`0xF04`-`0xF9C`	-	-	-	-	-
1000	`0xFA0`	RW	`0, c7, c8, 6`	RW	DBGCLAIMSET	Claim Tag Set Register
1001	`0xFA4`	RW	`0, c7, c9, 6`	RW	DBGCLAIMCLR	Claim Tag Clear Register
1002-1003	-	-	-	-	Reserved	-
1004	`0xFB0`	WO	No access	No access	DBGLAR	Lock Access Register
1005	`0xFB4`	RO	No access	No access	DBGLSR	Lock Status Register
1006	`0xFB8`	RO	`0, c7, c14, 6`	RO	DBGAUTHSTATUS	Authentication Status Register
1007-1008	-	-	-	-	Reserved	-
1009	`0xFC4`	RO	No access	No access	DBGDEVID1	-
1010	`0xFC8`	RO	No access	No access	DBGDEVID	-
1011	`0xFCC`	RO	No access	No access	DBGDEVTYPE	Device Type Register
1012-1016	`0xFD0`-`0xFEC`	RO	No access	No access	PERIPHERALID	CoreSight Identification Registers
1017-1019	-	-	-	-	Reserved	-
1020-1023	`0xFF0`-`0xFFC`	RO	No access	No access	COMPONENTID	CoreSight Identification Registers
^[a]Baseline CP14 interface. This register also has an external view through the memory-mapped interface and the CP14 interface. ^[b]Accessible in user mode if bit [12] of the DBGSCR is clear. Also accessible in privileged modes. ^[c]PMU registers are part of the CP15 interface. Reads from the extended CP14 interface return zero. See Register summary. See also Performance Monitoring Unit.

Debug register descriptions

This section describes register features specific to the Cortex-R7 MPCore processor. See the ARM Architecture Reference Manual for information about other register features not described in this section.

Debug Status and Control Register, DBGDSCR

Behaves as described in the ARM Architecture Reference Manual, except for the following bits:

PipeAdv, bit[25]: This bit is set each time a branch is resolved in the processor.
HALTED, bit[0]: This bit is the only bit of the register that is not reset on debug logic reset. It is reset to 1'b0 on a processor logic reset. Its behavior is as described in the ARM Architecture Reference Manual.

Debug Run Control Register, DBGDRCR

Behaves as described in the ARM Architecture Reference Manual, except for the following bits:

Cancel BIU Requests, bit[4]: Not implemented, RAZ/WI.
Bits[3:0]: Implemented as described in the ARM Architecture Reference Manual.

Device Powerdown and Reset Control Register, DBGPRCR

Behaves as described in the ARM Architecture Reference Manual, except for the following bits:

Bits[2:1]: Not implemented, RAZ/WI.
DBGnoPWRDWN, bit[0]: Implemented as described in the ARM Architecture Reference Manual (RW).

Device Powerdown and Reset Status Register, DBGPRSR

Behaves as described in the ARM Architecture Reference Manual, except for the following bits:

Sticky Reset Status, bit[3]: Implemented as described in the ARM Architecture Reference Manual.
Reset Status, bit[2]: Implemented as described in the ARM Architecture Reference Manual.
Sticky Powerdown Status, bit[1]: Not implemented, RAZ/WI.
Power-up Status, bit[0]: Implemented, RAO.

Breakpoint and Watchpoint Registers, DBGBVRn, DBGBCRn, DBGWVRn, and DBGWCRn

Behave as described in the ARM Architecture Reference Manual, except for the following:

Only BRP4 and BRP5 support context ID comparison.
BVR0[1:0], BVR1[1:0], BVR2[1:0], and BVR3[1:0] are SBZP on writes and RAZ on reads because these registers do not support context ID comparisons.
The context ID value for a BVR to match with is given by the contents of the CP15 Context ID Register.

Effects of resets on debug registers

nDBGRESET: nDBGRESET is the debug logic reset signal. This signal must be asserted during a powerup reset sequence.

On a debug reset:

The debug state is unchanged. That is, DBGSCR.HALTED is unchanged.
The processor removes the pending halting debug events DBGDRCR.HaltReq.

Debug management registers

The management registers define the standardized set of registers that is implemented by all CoreSight components. Table 10.9 shows the contents of the debug management registers for the Cortex-R7 debug unit. On the Cortex-R7 MPCore processor, the debug management registers are memory-mapped.

Table 10.9. Debug management registers

APB offset	Register number	Access	Mnemonic	Description
`0xD00-0xDFC`	832-895	RO	-	Processor ID Registers
`0xE00-0xEF0`	854-956	RAZ/WI	-	Not implemented
`0xF00`	960	RAZ/WI	ITCTRL	-
`0xF04-0xF9C`	961-999	RAZ/WI	-	Not implemented
`0xFA0`	1000	RW	CLAIMSET	-
`0xFA4`	1001	RW	CLAIMCLR	-
`0xFA8-0xFBC`	1002-1003	RAZ/WI	-	Not implemented
`0xFB0`	1004	WO	LOCKACCESS	-
`0xFB4`		RO	LOCKSTATUS	-
`0xFB8`		RO	AUTHSTATUS	-
`0xFBC-0xFC4`	1007-1009	RAZ/WI	-	Not implemented
`0xFC8`	1010	RO	DEVID	-
`0xFCC`	1011	RO	DEVTYPE	-
`0xFD0-0xFFC`	1012-1023	RO	-	CoreSight Identification Registers

Processor ID Registers

The Processor ID Registers are read-only registers that return the same values as the corresponding CP15 ID Code Register and Feature ID Register.

Table 10.10 shows the APB offset value, register number, mnemonic, and description that are associated with each Processor ID Register.

Table 10.10. Processor ID Registers

APB offset	Register number	Mnemonic	Access	Register value	Description
`0xD00`	832	MIDR	RO	-^[a]	Main ID Register alias
`0xD04`	833	CTR	RO	`0x8333C003`	Cache Type Register
`0xD08`	834	TCMTR	RO	-^[b]	TCM Type Register
`0xD0C`	835	MIDR	RO	-^[a]	Main ID Register alias
`0xD10`	836	MPUIR	RO	-^[c]	MPU Type Register
`0xD14`	837	MPIDR	RO	-^[d]	Multiprocessor Affinity Register
`0xD18`	838	REVIDR	RO	`0x0`	Revision ID Register
`0xD1C`	839	MIDR	RO	-^[a]	Main ID Register alias
`0xD20`	840	ID_PFR0	RO	`0x00000131`	Processor Feature Register 0
`0xD24`	841	ID_PFR1	RO	`0x00000001`	Processor Feature Register 1
`0xD28`	842	ID_DFR0	RO	`0x00010404`	Debug Feature Register 0
`0xD2C`	843	ID_AFR0	RAZ	-	Auxiliary Feature Register 0
`0xD30`	844	ID_MMFR0	RO	`0x00110130`	Memory Model Feature Register 0
`0xD34`	845	ID_MMFR1	RO	`0x0`	Memory Model Feature Register 1
`0xD38`	846	ID_MMFR2	RO	`0x01200000`	Memory Model Feature Register 2
`0xD3C`	847	ID_MMFR3	RO	`0x00002111`	Memory Model Feature Register 3
`0xD40`	848	ID_ISAR0	RO	`0x02101111`	Instruction Set Attribute Register 0
`0xD44`	849	ID_ISAR1	RO	`0x13112111`	Instruction Set Attribute Register 1
`0xD48`	850	ID_ISAR2	RO	`0x21232141`	Instruction Set Attribute Register 2
`0xD4C`	851	ID_ISAR3	RO	`0x01112131`	Instruction Set Attribute Register 3
`0xD50`	852	ID_ISAR4	RO	`0x00010142`	Instruction Set Attribute Register 4
`0xD54`	853	ID_ISAR5	RAZ	-	Instruction Set Attribute Register 5
^[a]`0x41nFC17m`: n = variant. m = revision. ^[b]TCM present = `0x80010001`.TCM not present = `0x0`. ^[c]MPU_16 configuration = `0x00001000`. MPU_12 configuration = `0x00000C00`. ^[d]Dependent on cluster and processor IDs: With one processor = `0x80000000`. With two processors = `0xC0000n0m`. `n` = CLUSTERID input. `m` = processor number (`0x0` for processor 0, `0x1` for processor 1.

CoreSight Identification Registers

The Identification Registers are read-only registers that consist of the Peripheral Identification Registers and the Component Identification Registers. The Peripheral Identification Registers provide standard information required by all CoreSight components. Only bits[7:0] of each register are used.

The Component Identification Registers identify the processor as a CoreSight component. Only bits[7:0] of each register are used, the remaining bits Read-As-Zero. The values in these registers are fixed.

Table 10.11 shows the APB offset value, register number, and description that are associated with each Peripheral Identification Register.

Table 10.11. Peripheral Identification Registers for processor debug

APB offset	Register number	Value	Description
`0xFD0`	1012	`0x04`	Peripheral Identification Register 4
`0xFD4`	1013	-	Reserved
`0xFD8`	1014	-	Reserved
`0xFDC`	1015	-	Reserved
`0xFE0`	1016	`0x17`	Peripheral Identification Register 0
`0xFE4`	1017	`0xBC`	Peripheral Identification Register 1
`0xFE8`	1018	`0x0B`	Peripheral Identification Register 2
`0xFEC`	1019	`0x00`	Peripheral Identification Register 3

Table 10.12 shows the APB offset value, register number, and value that are associated with each Component Identification Register.

Table 10.12. Component Identification Registers

APB offset	Register number	Value	Description
`0xFF0`	1020	`0x0D`	Component Identification Register 0
`0xFF4`	1021	`0x90`	Component Identification Register 1
`0xFF8`	1022	`0x05`	Component Identification Register 2
`0xFFC`	1023	`0xB1`	Component Identification Register 3

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