9.1. About multiprocessing and the SCU

The SCU connects Cortex-R7 processors to the memory system through the AXI3 interfaces. The SCU functions are to:


The Cortex-R7 SCU does not support hardware management of coherency of the instruction cache.

The SCU has an optional Accelerator Coherency Port (ACP) used to connect a non-cached master such as a DMA to the Cortex-R7 MPCore processor, as shown in Figure 9.1.

Figure 9.1. SCU and ACP

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The SCU has two slave ports per processor, one connected to the instruction bus and one connected to the data bus of each processor.

The data transfers on the ACP can be coherent in a multiprocessor implementation. The ACP also provides a noncoherent mode, where any transfer can be done directly with the level 2 memory directly, without having to deal with data coherency. See Coherent and noncoherent mode for information on coherent and noncoherent mode usage.

The data coherency efficiency, either using the ACP or between individual processors, is enhanced by using the replicated Tag RAMs of each L1 Data Cache Tag RAM of the individual processors in the multiprocessor implementation. Any transfer through the SCU is looked up in the replicated Tag RAM to determine whether data is present in the L1 data cache of either processor without having to access that cache. The replicated Tag RAM is an implementation of a directory structure.

You can choose to have one or two AXI master ports. The SCU also provides memory-mapped address filtering to enable you to route specific transfers on AXI master port 1 with QoS guarantees. See AXI master port 1 and System configurability and QoS.

The SCU also contains:

You can configure the individual processor event monitors to gather statistics on the operation of the SCU. See Performance Monitoring Unit.

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