2.3.3. Initialization

Most of the architectural registers in the Cortex-R7 MPCore processor, such as r0-r14, and s0-s31 and d0-d15 when floating-point is included, have an unknown value after reset. Because of this, you must initialize these for all modes before they are used, using an immediate-MOV instruction, or a PC-relative load instruction. The Current Program Status Register (CPSR) is given a known value on reset. This is described in the ARM® Architecture Reference Manual ARMv7-A and ARMv7-R edition. The reset values for the CP15 registers are described along with the registers in Chapter 4 System Control.

In addition, before you run an application, you might want to:

The following sections describe other initialization requirements:


Before you can use MPU you must:

Do not enable the MPU unless at least one MPU region is programmed and active. If the MPU is enabled, before using the TCM interfaces you must program MPU regions to cover the TCM regions to give access permissions to them.


If the Cortex-R7 MPCore processor has been built with an FPU, you must enable it before Vector Floating Point (VFP) instructions can be executed. Enable the FPU as follows:


If the Cortex-R7 MPCore processor has been built with instruction or data caches, they must be invalidated before they are enabled, otherwise unpredictable behavior can occur. See About the caches.

An invalidate all operation never reports any ECC errors. See Auxiliary Control Register.


The Cortex-R7 MPCore processor does not initialize the TCM RAMs, so you must initialize all the TCMs. In addition, you might want to preload instructions or data into the TCM for the main application to use. This section describes various ways that you can perform data preloading. You can also configure the Cortex-R7 MPCore processor to use the TCMs from reset. See Instruction and data TCM, DTCM Region Register and ITCM Region Register.

Preloading TCMs

You can write data to the TCMs using either store instructions or the AXI3 slave interface. Depending on the method you choose, you might require:

  • Particular hardware on the SoC that you are using.

  • Boot code.

  • A debugger connected to the processor.

Methods to preload TCMs include:

Memory copy with running boot code

The boot code includes a memory copy routine that reads data from a ROM, and writes it into the appropriate TCM. You must enable the TCM to do this, and it might be necessary to give the TCM one base address while the copy is occurring, and a different base address when the application is being run.

Copy data from the debug communications channel

The boot code includes a routine to read data from the Debug Communications Channel (DCC) and write it into the TCM. The debug host feeds the data for this operation into the DCC by writing to the appropriate registers on the processor APB debug port.

Execute code in debug halt state

The debug host puts the Cortex-R7 MPCore processor into debug halt state and then feeds instructions into it through the Instruction Transfer Register (DBGITR). The Cortex-R7 MPCore processor executes these instructions, that replace the boot code in either of the two methods previously described.

DMA into TCM

The SoC includes a Direct Memory Access (DMA) device that reads data from a ROM, and writes it to the TCMs through their AXI slave interfaces.

Preloading TCMs with ECC

The error code bits in the TCM RAM, if configured with an error scheme, are not initialized by the Cortex-R7 MPCore processor. Before a RAM location is read with ECC enabled, the error code bits must be initialized. To calculate the error code bits correctly, the logic must have all the data in the data chunk that those bits protect. Therefore, when the TCM is being initialized, the writes must be of the same width and aligned to the data chunk that the error scheme protects.

You can initialize the TCM RAM with error checking turned on or off, according to the following rules. See Auxiliary Control Register. You can use the ITCMECCEN signal to enable the ITCM when leaving reset.

If the slave port is used, for TCM memory accesses, the transactions must start at a 32-bit aligned address for data or 64-bit aligned address for instructions, and read or write a continuous block of memory, containing a multiple of 4 bytes for data or 8 bytes for instruction. All bytes in the block must be written, that is, have their byte lane strobe asserted.

If initialization is done by running code on the Cortex-R7 MPCore processor, this is best done by a loop of stores that write to the whole of the TCM memory as follows:

  • If the scheme is 32-bit ECC, use Store Word (STR), Store Two Words (STRD), or Store Multiple Words (STM) instructions to 32-bit aligned addresses.

  • If the scheme is 64-bit ECC, use STRD or STM, that has an even number of registers in the register list with a 64-bit aligned starting address.


You can use the alignment-checking features of the Cortex-R7 MPCore processor to help you ensure that memory accesses are 32-bit aligned, but there is no checking for 64-bit alignment. If you are using STRD or STM, an alignment fault is generated if the address is not 32-bit aligned. For the same behavior with STR instructions, enable strict-alignment-checking by setting the A-bit in the System Control Register. See System Control Register.

Using TCMs from reset

You can pin-configure the Cortex-R7 MPCore processor to enable the TCM interfaces from reset and to select the address at which each TCM appears from reset. This enables you to configure the processor to boot from TCM but, to do this, the TCM must first be preloaded with the boot code. The nCPUHALT input can be asserted while the processor is in reset to prevent the processor from fetching and executing instructions after coming out of reset. While the processor is halted in this way, the TCMs can be preloaded with the appropriate data. When the nCPUHALT input is deasserted, the processor starts fetching instructions from the reset vector address in the normal way.


When nCPUHALT has been deasserted to start the processor fetching, it must not be asserted again except when the processor is under processor or powerup reset. See Resets.

Copyright © 2012, 2014 ARM. All rights reserved.ARM DDI 0458C