10.3. Memory Reconstruction Port

The MRP is an optional feature on the Cortex-R7 MPCore processor. All write accesses, regardless of memory attributes, such as Strongly-Ordered, Device, Non-cacheable, and Cacheable, are exported from the processor through this port so that an image of the memory can be reconstructed. This port is intended for memory reconstruction only.

The MRP can be enabled using the Auxiliary Control Register.

The MRP has the following restrictions:

See Memory reconstruction port signals for a complete list of the MRP interface signals.

The ready signal of the SoC slave is used to drive the ready signal of the store buffer towards the LSU. As a result, asserting this signal LOW directly impacts the performance of the processor, and writes are kept in the LSU until the SoC can execute the incoming writes. You can use a FIFO to provide limited and reasonable back-pressure on the ready signal.

Note

There is no response channel on the MRP. Any possible dec/slave error is reported by the normal AXI channel.

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