2.3.2. Resets

The Cortex-R7 MPCore processor has the following reset signals, where N is 1 or 2:

The following reset signals are present for CoreSight debug logic:

The following reset signals are present if ETM0 is present:

The following reset signals are present if ETM1 is present:

The following additional reset signals are present if lock-step or split/lock is implemented:

The reset signals in the Cortex-R7 MPCore processor design enable you to reset different parts of the design independently. Table 2.1 shows the supported reset combinations in a Cortex-R7 system. [n] refers to the processor that receives a reset.

Table 2.1. Reset combinations in a Cortex-R7 system

Reset signalsCortex-R7 MPCoreIndividual processorsCortex-R7 MPCore debugIndividual processors
PowerupSoftwarePowerupSoftwareDebugWatchdog flag
nSCURESET and nPERIPHRESET0011111
nCPURESET[1:0]All 0All 0[n]=0[n]=0All 1All 1All 1
nDBGRESET[1:0]All 0All 1[n]=0All 1All 0[n]=0All 1
nWDRESET[1:0]All 0All 0[n]=0 or all 1[n]=0 or all 1All 1All 1[n]=0

See Clock and control signals and Reset signals.

The following sections describe the reset sequences:

Cortex-R7 MPCore powerup reset

You must apply powerup or cold reset to the Cortex-R7 MPCore processor when power is first applied to the system. In the case of powerup reset, the leading edge, that is the falling edge, of the reset signals do not have to be synchronous to CLK, but the rising edge must be. You must assert the reset signals for at least 10 CLK cycles to ensure correct reset behavior.

You must generate DUALPERIPHCLK, DUALPERIPHCLKEN, and DUALPERIPHCLKOFF as delayed versions of the equivalent primary core signals. Use the same delay as between the primary core and the redundant core.

ARM recommends the following reset sequence:

  1. Apply nCPURESET, nDBGRESET, nWDRESET, nSCURESET, nPERIPHRESET, nCTRESET, nETM0RESET if ETM0 is present, and nETM1RESET if ETM1 is present.

  2. Wait for at least 10 CLK cycles, or more if required by other components. There is no harm in applying more clock cycles than this, and maximum redundancy can be achieved by, for example, applying 15 cycles on every clock domain.

  3. Stop the CLK clock input to the Cortex-R7 MPCore processor. You can use an integrated clock gating cell driven by a reset controller to stop the CLK.

  4. Wait for the equivalent of approximately 10 cycles, depending on your implementation. This compensates for clock and reset tree latencies.

  5. Release all resets.

  6. Wait for the equivalent of approximately 10 cycles to compensate for clock and reset tree latencies.

  7. Restart the CLK clock input.

For a lock-step or split/lock implementation, use the following reset sequence:

  1. Apply nCPURESET, nDBGRESET, nWDRESET, nSCURESET, nPERIPHRESET, nCTRESET, nETM0RESET if ETM0 is present, and nETM1RESET if ETM1 is present.

  2. Wait for at least 10 CLK cycles, or more if required by other components. There is no harm in applying more clock cycles than this, and maximum redundancy can be achieved by, for example, applying 10 cycles on every clock domain.

  3. Drive DUALPERIPHCLKOFF, SCUCLKOFF, and PERIPHCLKOFF HIGH.

  4. Stop the CLK clock input to the Cortex-R7 MPCore processor.

  5. Wait for the equivalent of approximately 10 cycles, depending on your implementation. This compensates for clock and reset tree latencies.

  6. Release all resets.

  7. Wait for the equivalent of approximately 10 cycles, to compensate for clock and reset tree latencies.

  8. Restart the CLK clock and maintain DUALPERIPHCLKOFF HIGH.

    SCUCLKOFF and PERIPHCLKOFF are driven LOW. If you want to, you can maintain these two signals HIGH a few more clock cycles but this is not required.

  9. After P* CLK cycles, after PERIPHCLKOFF is driven low, drive DUALPERIPHCLKOFF LOW.

Note

P* is defined by the number of delay cycles introduced between the main processor and the dual-redundant processor. It is configurable and implementation defined. The default value used in the Cortex-R7 MPCore processor is 2.

Individual processor powerup reset

This reset is for the processor 0 or processor 1 level. It initializes the whole logic in a single processor, including its debug logic. It is expected to be applied when this individual processor exits from powerdown or dormant state. This reset only applies to configurations where each individual processor is implemented in its own power domain.

The reset sequence is as follows:

  1. Apply nCPURESET[n] and nDBGRESET[n]. You can apply the nWDRESET[n] reset if you want to reset the corresponding watchdog flag.

  2. Wait for at least 10 CLK cycles, or more if required by other components. There is no harm in applying more clock cycles than this.

  3. Assert CPUCLKOFF[n] and DBGCLKOFF[n] with a value of 1’b1.

  4. Wait for the equivalent of approximately 10 cycles, depending on your implementation. This compensates for clock and reset tree latencies.

  5. Release all resets.

  6. Wait for the equivalent of approximately 10 cycles, to compensate for clock and reset tree latencies.

  7. Deassert CPUCLKOFF[n] and DBGCLKOFF[n]. This ensures that all registers in the processor see the same CLK edge on exit from the reset sequence.

The individual processor powerup reset can be extended to enable its corresponding ETM to be powered down. To wake up from powerdown or dormant mode with ETM, use the nETM[n]RESET and ETM[n]CLKOFF signals in the same way as nCPURESET[n] and CPUCLKOFF[n].

Note

When resetting a processor from a powerdown state while the ETM is not reset, ARM recommends that you disable the ETM using the APB port before resetting the processor. This avoids the risk of tracing bad data at the point when the processor is reset.

Individual processor software reset

This reset is for the processor 0 or processor 1 level, without debug logic. It initializes all functional logic in a single individual processor apart from its debug logic. All breakpoints and watchpoints are retained during this individual warm reset. This reset only applies to configuration where each individual processor is implemented in its own power domain.

ARM recommends that you use the reset sequence described in Individual processor powerup reset, except that nDBGRESET, nCTIRESET, and nETMxRESET must not be asserted during the sequence. This ensures that the debug registers of the individual processors retain their values.

Cortex-R7 MPCore debug reset

This reset initializes the debug logic in all processors present in the cluster. To perform a Cortex-R7 MPCore debug reset, assert all nDBGRESET signals for a number of CLK cycles. CPUCLKOFF, and ETM[0/1]CLKOFF if the ETM is present, must remain deasserted during this reset sequence.

Individual processor debug reset

This reset initializes the debug logic in an individual processor in the cluster. To perform an individual processor debug reset, assert the corresponding nDBGRESET[n] signal for a number of CLK cycles. CPUCLKOFF, and ETM[n]CLKOFF if the ETM is present, must remain deasserted during this reset sequence.

Note

When lock-step or split/lock is implemented, the software must clear the INTdis bit of the Debug Status and Control Register (DBGDSCR) before applying a debug reset. This is because if a pending interrupt is masked by the INTdis bit and a debug reset occurs, this bit is cleared by the reset and the interrupt is taken immediately by both processors on the same clock cycle.

Individual processor watchdog flag reset

This reset clears the watchdog flag associated with a single individual processor. Watchdog functionality is independent of all other processor functionality, so this reset is independent of the all other resets.

Note

When a watchdog reset request occurs and when lock-step or split/lock is implemented, the reset must not be applied immediately to the entire Cortex-R7 MPCore processor. This is because after reset the sticky flag is set in one processor, but not the other and this leads to the assertion of COMPFAULT. Therefore, if one processor has its watchdog flag set, the other processor must reach the same state, that is, also having its watchdog flag set. This can be controlled using the PERIPHCLKOFF and DUALPERIPHCLKOFF signals.

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