1.6.1. Split/lock

If two Cortex-R7 processors are included and the Split/lock infrastructure implemented, the processor group can operate in one of two modes:

Split mode

Operates as a multiprocessor configuration, with both processors capable of doing multiprocessing, by maintaining L1 data cache coherency. Each processor uses its dedicated cache RAM. Also known as performance mode.

Locked mode

Operates in lock-step mode. The second processor works as redundant logic for the individual processor logic, and the SCU logic, but not the ETM logic if the ETM is present. The processor 1 side cache RAM remains implemented but not used.

You can select the usage mode with the SAFEMODE input signal. This input can be changed only while the processor group is held in reset and must remain stable when out of reset.

For more information about how to make a change in processor mode, contact your system integrator.

If you are implementing a Split/lock configuration, contact ARM for more information.

Copyright © 2012, 2014 ARM. All rights reserved.ARM DDI 0458C