4.3.14. ITCM Region Register

The ITCMRR characteristics are:

Purpose
  • Indicates the base address and size of the Instruction TCM.

  • Enables the Instruction TCM directly from reset.

Usage constraints

The ITCMRR is :

  • Only accessible in privileged mode.

  • For use with INITRAM0.

Configurations

Available in all configurations.

Attributes

See the register summary in Table 4.7.

Figure 4.16 shows the ITCMRR bit assignments.

Figure 4.16. ITCMRR bit assignments

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Table 4.34 shows the ITCMRR bit assignments.

Table 4.34. ITCMRR bit assignments

BitsNameFunction
[31:12]Instruction TCM region base address

Indicates the Instruction TCM region base address.

When INITRAM0 is HIGH and VINITH0 is HIGH for processor 0, the reset value is 0xFFFF0, otherwise the reset value is 0x00000.

The same applies for processor 1, if present.

[11:6]-SBZ
[5:2]Instruction TCM size

Indicates the Instruction TCM region size:

0b0000

0KB.

0b0011

4KB.

0b0100

8KB.

0b0101

16KB.

0b0110

32KB.

0b0111

64KB.

0b1000

128KB.

All other values are Reserved.

[1]-SBZ
[0]Enable bit

Enable bit:

0

Disabled. This is the reset value.

1

Enabled.

When INITRAM0 is HIGH this enables the Instruction TCM for processor 0 directly from reset.

The same applies for processor 1, if present. When INITRAM1 is HIGH, this enables the Instruction TCM for processor 1 directly from reset.

If Instruction TCM is not implemented, this field is Read-only and its value is 0.


To access the ITCMRR, read or write the CP15 register with:

MRC p15, 0, <Rd>, c9, c1, 1; Read ITCM Region Register
MCR p15, 0, <Rd>, c9, c1, 1; Write ITCM Region Register
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