2.5.1. AXI master port 0

This port has optional ECC protection on data and parity on control bits, see ECC on external AXI bus.

This port does not support AXI locked writes, that is, AWLOCKM0[1] is always 0.

This port supports five bits of AXI IDs, although AXI IDs can be larger if the ACP has more than four bits of ID. For example, if the ACP ID has 4 bits, there are 5 bits on the AXI master port. If the ACP ID has 8 bits, there are 9 bits on the AXI master port.

Note

  • ID bit encoding is used to differentiate between different types of traffic happening in parallel. The encoding of the IDs is implementation-specific.

  • You can use the AxUSER buses to identify the origin of the traffic, that is, processor 0, processor 1, or the ACP.

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