2.5.2. AXI master port 1

This port is optional, and has optional ECC protection on data and parity on control bits, see ECC on external AXI bus. It has an address filtering feature enabled by the SCU Control Register. When the master address filtering is enabled through the MFILTEREN input or the SCU Control Register, any access in the address range between the master filtering start address and the master filtering end address is issued on AXI master port 1. All other accesses outside of this range are directed onto AXI master port 0. The start and end addresses are configurable in the following SCU registers:

The granularity of the mapped memory is 1MB using the following formula:

Memory_space (MB) = Start to End + 1.

This filtering rule is applied independently of the AXI request type and attributes.

When master address filtering is disabled, accesses can be issued on either AXI master port 0 or AXI master port 1, if the AXI ordering rules are respected. In this case, locked and exclusive accesses are always issued on AXI master port 0.

This port does not support locked writes, that is, AWLOCKM1[1] is always 0.

This port supports five bits of AXI IDs, although AXI IDs can be larger if the ACP has more than four bits of ID. For example, if the ACP ID has 4 bits, there are 5 bits on the AXI master port. If the ACP ID has 8 bits, there are 9 bits on the AXI master port.

Note

ID bit encoding is used to differentiate between different types of traffic happening in parallel. The encoding of the IDs is implementation-specific.

If you connect an L2 cache controller to AXI master port 0 and AXI master port 1, you cannot enable address filtering on AXI master port 1. There is no restriction on enabling address filtering on the AXI peripheral port. Some L2 cache controllers, such as the CoreLink Level 2 Cache Controller, can enable their own address filtering.

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