4.3.16. Cache and TCM Debug Operation Register

The CTDOR characteristics are:

Purpose

Describes the access operation required for cache and TCM debug.

Usage constraints

The CTDOR is write accessible in privileged mode only.

Configurations

Available in all configurations.

Attributes

See the register summary in Table 4.9.

Figure 4.18 shows CTDOR bit assignments for cache RAMs.

Figure 4.18. CTDOR bit assignments for cache RAMs

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Table 4.36 shows the CTDOR bit assignments for cache RAMs.

Table 4.36. CTDOR bit assignments for cache RAMs

BitsNameFunction
[31:30]Way selector

Indicates the way to select in the cache.

0b00

Way 0.

0b01

Way 1.

0b10

Way 2.

0b11

Way 3.

[29:23]-RAZ/WI.
[22]Select cache RAMs or TCMs
0

Use with cache RAMs.

[21]Select tag or data RAMs
0

Use with tag RAMs.

1

Use with data RAMs.

[20]Select data or instruction side
0

Select data side.

1

Select instruction side.

[19:14]-RAZ/WI.
[13:5]Cache indexIndicates the cache index.
[4:2]Word in data RAM

Indicates the 32-bit word in the cache line.

Only required if accessing data RAM.

[1]-RAZ/WI.
[0]Select read or write operation
0

Read operation.

1

Write operation.


Figure 4.19 shows the CTDOR bit assignments for TCM RAMs.

Figure 4.19. CTDOR bit assignments for TCMs

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Table 4.37 shows the CTDOR bit assignments for TCM RAMs.

Table 4.37. CTDOR bit assignments for TCMs

BitsNameFunction
[31:23]-RAZ/WI.
[22]Select cache or TCM RAMs
1

Use with TCMs.

[21]-RAZ/WI.
[20]Select data or instruction side
0

Select data side.

1

Select instruction side.

[19:17]-RAZ/WI.
[16:2]Address

Indicates the address of the TCM RAM.

[1]-RAZ/WI.
[0]Select read or write operation
0

Read operation.

1

Write operation.


To access the CTDOR, read or write the CP15 register with:

MRC p15, 0, <Rd>, c15, c1, 0 ; Read Cache and TCM Debug Operation Register
MCR p15, 0, <Rd>, c15, c1, 0 ; Write Cache and TCM Debug Operation Register
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