8.5. System configurability and QoS

You can use the Quality of Service (QoS) to ensure that low priority cacheable traffic does not block the flow of accesses from peripherals and AXI master port 1.

Caution

If the processor uses the QoS feature and address filtering is enabled for AXI master port 1, the slave connected to AXI master port 1 must be private to the processor. When QoS is not enabled, no such system constraint exists.

A real-time system with two AXI3 master ports and address filtering can stream critical tasks and background tasks so that the flow of background tasks, particularly cached low priority tasks, that can have significant memory latency, does not block the flow of critical tasks:

The QoS bit in the Auxiliary Control Register is used to enable QoS:

The QoS bit can be used to ensure that low priority cacheable traffic does not block the flow of accesses from the following:

You can set the QoS bit on a per processor basis to ensure that low priority cacheable traffic with significant memory latencies does not block the flow of traffic from these tasks. The SCU offers some QoS as soon as the filtering is enabled on AXI master port 1.

You can use the QoS bit to set different mixes of traffic flows:

Table 8.5 shows the recommended QoS bit settings according to traffic types.

Table 8.5. Recommended QoS bit settings according to traffic types

Traffic flow typesLow priority cacheable traffic types
Small and bounded memory latencyPotentially large and unbounded memory latency
Peripheral and TCM traffic only.Do not set QoS bitDo not set QoS bit
Peripheral and low priority cacheable traffic, the TCM can be present or not, and low priority traffic is on AXI master port 0.Do not set QoS bitSet QoS bit
Peripheral traffic, low and high priority cacheable traffic, the TCM can be present or not, and low priority traffic is on AXI master port 0, with high priority traffic on AXI master port 1.Do not set QoS bitSet QoS bit

The recommendations in Table 8.5 make the following assumptions:

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