4.3.10. Auxiliary Control Register

The ACTLR characteristics are:

Purpose

Controls:

  • QoS settings.

  • ECC checking, if implemented.

  • Allocation in one way.

  • Automatic data cache coherency.

  • Speculative accesses on AXI.

  • Broadcast of cache, branch predictor, and maintenance operations.

  • Enabling the MRP, if implemented.

Usage constraints

The ACTLR is only accessible in privileged mode.

Configurations

Available in all configurations.

  • When the SMP bit = 0, Inner Cacheable Shareable attributes are treated as Non-cacheable.

  • When the SMP bit is set:

    • Broadcasting cache maintenance operations is permitted if the FW bit is set.

    • Receiving cache maintenance operations broadcast by other Cortex-R7 processors in the same coherent cluster is permitted if the FW bit is set.

    • The Cortex-R7 processor can send and receive coherent requests for Shareable Inner Write-back Write-Allocate accesses from the other Cortex-R7 processors in the same coherent cluster.

Attributes

See the register summary in Table 4.3.

Figure 4.9 shows the ACTLR bit assignments.

Figure 4.9. ACTLR bit assignments

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Table 4.26 shows the ACTLR bit assignments.

Table 4.26. ACTLR bit assignments

BitsNameFunction
[31:12]-UNP/SBZP
[11]QoS

Quality of Service bit

0

Disabled. This is the reset value.

1

Enabled.

See System configurability and QoS.

[10]ECC on ITCM

Support for ECC on ITCM, if implemented:

0

Disabled.

1

Enabled.

The reset value is defined by the ITCMECCEN signal. If ECC is not implemented this bit is RAZ/WI.

[9]ECC on caches and DTCM

Support for ECC on instruction and data cache and DTCM, if implemented:

0

Disabled. This is the reset value.

1

Enabled.

If ECC is not implemented this bit is RAZ/WI.

[8]Alloc in one wayEnable allocation in one cache way only. For use with memory copy operations to reduce cache pollution. The reset value is zero.
[7]-SBZ
[6]SMP

Signals if the Cortex-R7 processor is taking part in coherency or not.

If this bit is set, then Inner Write Back Shareable is treated as Cacheable. The reset value is zero.

[5:4]-RAZ/WI
[3]MRP enable

MRP enable:

0

Disabled. This is the reset value.

1

Enabled.

[2:1]-SBZ
[0]FW

Cache maintenance broadcast:

0

Disabled. This is the reset value.

1

Enabled.

RAZ/WI if only one Cortex-R7 processor is present.


To access the ACTLR, read or write the CP15 register with:

MRC p15, 0, <Rd>, c1, c0, 1; Read ACTLR
MCR p15, 0, <Rd>, c1, c0, 1; Write ACTLR
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