8.2. Memory Protection Unit

The MPU works with the L1 memory system to control accesses to and from L1 and external memory. For a full architectural description of the MPU and the memory map, see the ARM® Architecture Reference Manual ARMv7-A and ARMv7-R edition.

The MPU enables you to partition memory into regions and set individual protection attributes for each region. The MPU supports 12 or 16 memory regions, depending on the configuration. See the ARM® Cortex®-R7 MPCore Configuration and Sign-off Guide.

Each region is programmed with a base address and size, and the regions can be overlapped to enable efficient programming of the memory map. To support overlapping, the regions are assigned priorities, with region 0 having the lowest priority and region 11 or 15 having the highest priority respectively when 12 or 16 memory regions are supported. The MPU returns access permissions and attributes for the highest priority region where the address hits.

The MPU is programmed using CP15 registers c1 and c6, see MPU memory region programming registers. Memory region control read and write access is permitted only from privileged modes.

This section describes:

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