4.3.11. Coprocessor Access Control Register

The CPACR characteristics are:

Purpose
  • Sets access rights for the coprocessors CP11 and CP10.

  • Enables software to determine if any particular coprocessor exists in the system.

Note

This register has no effect on access to CP14 or CP15.

Usage constraints

The CPACR is only accessible in privileged mode.

Configurations

Available in all configurations.

Attributes

See the register summary in Table 4.3.

Figure 4.10 shows the CPACR bit assignments.

Figure 4.10. CPACR bit assignments

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Table 4.27 shows the CPACR bit assignments.

Table 4.27. CPACR bit assignments

BitsNameFunction
[31:24]-RAZ/WI.
[23:22]cp11

Defines access permissions for CP11:

0b00

Access denied. This is the reset value, and the behavior for nonexistent coprocessors. Attempted access generates an Undefined Instruction exception.

0b01

Privileged mode access only.

0b10

Reserved.

0b11

Privileged and user mode access.

[21:20]cp10

Defines access permissions for CP10:

0b00

Access denied. This is the reset value, and the behavior for nonexistent coprocessors. Attempted access generates an Undefined Instruction exception.

0b01

Privileged mode access only.

0b10

Reserved.

0b11

Privileged and user mode access.

[19:0]-RAZ/WI.

To access the CPACR, read or write the CP15 register with:

MRC p15, 0, <Rd>, c1, c0, 2; Read Coprocessor Access Control Register
MCR p15, 0, <Rd>, c1, c0, 2; Write Coprocessor Access Control Register

You must execute an ISB immediately after an update of the CPACR. See Memory Barriers in the ARM® Architecture Reference Manual ARMv7-A and ARMv7-R edition. You must not attempt to execute any instructions that are affected by the change of access rights between the ISB and the register update.

To determine if any particular coprocessor exists in the system, write the access bits for the coprocessor of interest with 0b11. If the coprocessor does not exist in the system the access rights remain set to 0b00.

Note

You must enable both CP10 and CP11 before accessing any VFP system registers. If the access control bits are programmed differently for CP10 and CP11, operation of VFP features is unpredictable. This behavior is applicable for both FPU modes, that is, full or optimized.

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