4.3.6. Cache Level ID Register

The CLIDR characteristics are:

Purpose

Indicates the cache levels that are implemented in the Cortex-R7 MPCore processor and under the control of the System Control Coprocessor. If caches are not implemented, this register value is 0.

Usage constraints

The CLIDR is:

  • Only accessible in privileged mode.

  • A read-only register.

Configurations

Available in all configurations.

Attributes

See the register summary in Table 4.2.

Figure 4.6 shows the CLIDR bit assignments.

Figure 4.6. CLIDR bit assignments

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Table 4.23 shows the CLIDR bit assignments.

Table 4.23. CLIDR bit assignments

BitsNameFunction
[31:30]-UNP or SBZ
[29:27]LoU
0b001

Level of unification.

[26:24]LoC
0b001

Level of coherency.

[23:21]LoUIS
0b001

Level of Unification Inner Shareable.

[20:18]CL 7
0b000

No cache at CL 7.

[17:15]CL 6
0b000

No cache at CL 6.

[14:12]CL 5
0b000

No cache at CL 5.

[11:9]CL 4
0b000

No cache at CL 4.

[8:6]CL 3
0b000

No cache at CL 3.

[5:3]CL 2
0b000.

No unified cache at CL 2

[2:0]CL 1
0b000

Caches not implemented.

0b011

Separate instruction and data caches at CL 1.


To access the CLIDR, read the CP15 register with:

MRC p15, 1,<Rd>, c0, c0, 1; Read CLIDR
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