4.3.9. System Control Register

The SCTLR characteristics are:

Purpose

Provides control and configuration of:

  • Memory alignment and endianness.

  • Memory protection and fault behavior.

  • MPU and cache enables.

  • Interrupts and behavior of interrupt latency.

  • Location for exception vectors.

  • Program flow prediction.

Usage constraints

The SCTLR is only accessible in privileged mode.

Configurations

Available in all configurations.

Attributes

See the register summary in Table 4.3.

Figure 4.8 shows the SCTLR bit assignments.

Figure 4.8. SCTLR bit assignments

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Table 4.25 shows the SCTLR bit assignments.

Table 4.25. SCTLR bit assignments

Bits

NameAccess

Function

[31]--RAZ/SBZP.
[30]TERW

Thumb exception Enable:

0

Exceptions including reset are handled in ARM state.

1

Exceptions including reset are handled in Thumb state.

The TEINIT signal defines the reset value.

[29:28]--RAZ/SBZP.
[27]NMFIRO

Nonmaskable FIQ support.

The bit cannot be configured by software.

The CFGNMFI signal defines the reset value.

[26]--RAZ/SBZP.
[25]EERW

Exception Endianness. This bit determines how the E bit in the CPSR is set on an exception:

0

CPSR E bit is set to 0 on an exception.

1

CPSR E bit is set to 1 on an exception.

The CFGEND signal defines the reset value.

[24]--

RAZ/WI.

[23:22]

-

-RAO/SBOP.
[21]FIRW

Fast Interrupts configuration enable bit.

This bit can be used to reduce interrupt latency. The permitted values of this bit are:

0

All performance features enabled. This is the reset value.

1

Low interrupt latency configuration. Some performance features disabled.

[20]--RAZ/SBZP.
[19]DZRW

Divide by Zero fault enable bit.

This bit controls whether an integer divide by zero causes an undefined Instruction exception:

0

Divide by zero returns the result zero, and no exception is taken. This is the reset value.

1

Attempting a divide by zero causes an undefined Instruction exception on the SDIV or UDIV instruction.

[18]--RAO/SBOP.
[17]BRRW

Background Region bit.

When the MPU is enabled this bit controls how an access that does not map to any MPU memory region is handled:

0

Any access to an address that is not mapped to an MPU region generates a Background Fault memory abort. This is the reset value.

1

The default memory map is used as a background region:

  • A privileged access to an address that does not map to an MPU region takes the properties defined for that address in the default memory map.

  • An unprivileged access to an address that does not map to an MPU region generates a Background Fault memory abort.

[16]--RAO/SBOP.
[15]--RAZ/SBZP.
[14]--RAZ/WI.
[13]VRW

Vectors bit. This bit selects the base address of the exception vectors:

0

Normal exception vectors, base address 0x00000000.

1

High exception vectors, Hivecs, base address 0xFFFF0000.

At reset the value of this bit is taken from VINITHI.

[12]

I[a]

-

Determines if instructions can be cached at any available cache level:

0

Instruction caching disabled at all levels. This is the reset value.

1

Instruction caching enabled.

[11]

Z

RW

Enables program flow prediction:

0

Program flow prediction disabled. This is the reset value.

1

Program flow prediction enabled.

[10]SWRW

SWP/SWPB enable bit:

0

SWP and SWPB are undefined. This is the reset value.

1

SWP and SWPB perform normally.

[9:7]--RAZ/SBZP.
[6:3]--RAO/SBOP.
[2]

C[a]

RW

Determines if data can be cached at any available cache level:

0

Data caching disabled at all levels. This is the reset value.

1

Data caching enabled.

[1]

A

RW

Enables strict alignment of data to detect alignment faults in data accesses:

0

Strict alignment fault checking disabled. This is the reset value.

1

Strict alignment fault checking enabled.

Any unaligned access to Device or Strongly Ordered memory generates an alignment fault and therefore does not cause any peripheral interface access. This means that the access examples given in this manual never show unaligned accesses to Device or Strongly Ordered memory.

[0]

M

RW

Enables the MPU:

0

MPU disabled. This is the reset value.

1

MPU enabled.

[a] RW if caches implemented, RAZ/WI if no caches.


Attempts to modify read-only bits are ignored.

To access the SCTLR, read or write the CP15 register with:

MRC p15, 0, <Rd>, c1, c0, 0; Read SCTLR
MCR p15, 0, <Rd>, c1, c0, 0; Write SCTLR
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