A.17. Power gating interface signals

Table A.54 shows the power gating interface signals. x in the signal name represents either processor 0 or processor 1.

Table A.54. Power gating interface signals

NameTypeSource/destinationDescription
nPWRUPSCURAMInputPower controllerSCU power switch enable
nPWRUPACKSCURAMOutput SCU power switch acknowledge
nPWRUPCPUxInput Individual processor power switch enable
nPWRUPACKCPUxOutput Individual processor power switch acknowledge
nPWRUPCPUDRAMxInput Individual processor data RAM power switch enable
nPWRUPACKCPUDRAMxOutput  Individual processor data RAM power switch acknowledge
nPWRUPCPUIRAMxInput Individual processor instruction RAM power switch enable
nPWRUPACKCPUIRAMxOutput Individual processor instruction RAM power switch acknowledge
nPWRUPDTCMxInput Individual DTCM RAM power switch enable
nPWRUPACKDTCMxOutput Individual TCM RAM power switch acknowledge
nPWRUPITCMxInput Individual ITCM RAM power switch enable
nPWRUPACKITCMxOutput Individual TCM RAM power switch acknowledge
nPWRUPDBGInput  Debug power switch enable
nPWRUPACKDBGOutput  Debug power switch acknowledge
nPWRUPETMxInput Individual ETM power switch enable
nPWRUPACKETMxOutput Individual ETM power switch acknowledge
nISOLATESCURAMInput SCU RAM clamp control
nISOLATECPUxInput Individual processor clamp control
nISOLATECPUDRAMxInput Individual processor data RAM clamp control
nISOLATECPUIRAMxInput  Individual processor instruction RAM clamp control
nISOLATEDTCMxInput  Individual DTCM RAM clamp control
nISOLATEITCMxInput Individual ITCM RAM clamp control
nISOLATEDBGInput Debug clamp control
nISOLATEETMxInput  Individual ETM clamp control

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