4.3.5. Cache Size ID Register

The CCSIDR characteristics are:

Purpose

Provides information about the architecture of the caches selected by CSSELR.

Usage constraints

The CCSIDR is only accessible in privileged mode.

Configurations

Available in configurations with caches implemented. If caches are not implemented, the value of this register is unknown.

Attributes

See the register summary in Table 4.2.

Figure 4.5 shows the CCSIDR bit assignments.

Figure 4.5. CCSIDR bit assignments

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Table 4.22 shows the CCSIDR bit assignments.

Table 4.22. CCSIDR bit assignments

BitsNameFunction

[31]

WT

Indicates support available for Write-Through:

Set to 0

Write-Through support not available.

[30]

WB

Indicates support available for Write-Back:

0

Write-Back support not available.

1

Write-Back support available.

[29]

RA

Indicates support available for read allocation:

0

Read allocation support not available.

1

Read allocation support available.

[28]

WA

Indicates support available for write allocation:

0

Write allocation support not available.

1

Write allocation support available.

[27:13]

NumSets

Indicates number of sets:

0x1F

4KB cache size.

0x3F

8KB cache size.

0x7F

16KB cache size.

0xFF

32KB cache size.

0x1FF

64KB cache size.

[12:3]

Associativity

Indicates number of ways:

0b0000000011

Four ways.

[2:0]

LineSize

Indicates number of words:

0b001

Eight words per line.


To access the CCSIDR, read the CP15 register with:

MRC p15, 1, <Rd>, c0, c0, 0; Read current Cache Size Identification Register

If the CSSELR reads the instruction cache values and caches are implemented, bits[31:28] are 0b0010.

If the CSSELR reads the data cache values and caches are implemented, bits[31:28] are 0b0111. See Cache Size Selection Register.

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