8.6. Instruction and data TCM

Instruction and data TCMs are tightly-coupled in the Cortex-R7 MPCore processor. There are no external ports for the TCMs and only SRAM memory is supported. Instructions cannot be stored in the Data TCM. An instruction fetch to the Data TCM goes to the AXI interface and not the Data TCM. ARM recommends that the DTCM memory region is marked as XN in the MPU region settings to prevent instruction accesses to this address range.

There is an option to permit a single wait state on the instruction TCM. The data TCM does not accommodate wait states.

You can configure the instruction and data TCM size and the optional instruction TCM wait state during integration. See the ARM® Cortex®-R7 MPCore Integration Manual for more information. The permissible TCM sizes are:

Both TCMs can be preloaded using the AXI slave port. This slave port provides access to the TCMs only. See AXI TCM slave port.

From a programmer’s view:

Both instruction and data TCM are ECC protected. For more information, see ECC on RAMs.


Write accesses to the instruction TCM are possible for debug purposes, but with limited throughput.

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