4.3.8. Cache Size Selection Register

The CSSELR characteristics are:

Purpose

Selects the current CCSIDR.

Usage constraints

The CSSELR is only accessible in privileged mode.

Configurations

Available in all configurations.

Attributes

See the register summary in Table 4.2.

Figure 4.7 shows the CSSELR bit assignments.

Figure 4.7. CSSELR bit assignments

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Table 4.24 shows the CSSELR bit assignments.

Table 4.24. CSSELR bit assignments

BitsNameFunction
[31:4]-UNP or SBZ.
[3:1]Level

Cache level selected, RAZ/WI.

There is only one level of cache in the Cortex-R7 MPCore processor so the value for this field is 0b000.

[0]InD
1

Instruction cache.

0

Data cache.


To access the CSSELR, read the CP15 register with:

MRC p15, 2, <Rd>, c0, c0, 0; Read CSSELR
MCR p15, 2, <Rd>, c0, c0, 0; Write CSSELR
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