A.12. Test interface

Table A.40 shows the test interface signals.

Table A.40. Test interface signals

NameTypeSource/destinationDescription
DFTSEInputExternal test interface Scan shift enable
DFTRAMHOLDInputHolds RAM content during scan shift
DFTRAMCLKENABLEInputForces RAM clock for DFT purposes even when processors are in WFI mode
DFTTESTMODEInputDisable/bypass logic for test purposes

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