A.8.2. AXI peripheral port signals

Table A.14 shows the AXI peripheral port clock enable signals.

Table A.14. Clock enable signals

NameTypeSource/destinationDescription
INCLKENMPInputCLK

Clock enable

OUTCLKENMPInput

Clock enable


Table A.15 shows the AXI peripheral port read address signals.

Table A.15. AXI peripheral port read address signals

NameTypeSource/destinationDescription
ARADDRMP[31:0]OutputAXI3 deviceAddress.
ARBURSTMP[1:0]OutputBurst type.
ARCACHEMP[3:0]OutputCache type.
ARIDMP[n][a]OutputAddress ID.
ARLENMP[3:0]OutputBurst length.
ARLOCKMP[1:0]OutputLock type.
ARPROTMP[2:0]OutputProtection type.
ARREADYMPInputAddress ready.
ARSIZEMP[1:0]OutputBurst size.
ARUSERMP[8:0]OutputTransfer attributes. See AXI3 USER bits.
ARVALIDMPOutputAddress valid.

[a] You can define the number of AXI ID bits on this port using the AXISC_ID_BIT build parameter. If the ACP is implemented, [n] is [AXISC_ID_BIT:0], that is, the number of ACP ID bits + 1. If the ACP is not implemented, [n] is [4:0].


Table A.16 shows the AXI peripheral port read data signals.

Table A.16. AXI peripheral port read data signals

NameTypeSource/destinationDescription
RVALIDMPInputAXI3 deviceRead valid
RREADYMPOutputRead ready
RIDMP[n][a]InputRead ID
RLASTMPInputRead last
RDATAMP[31:0]InputRead data
RRESPMP[1:0]InputRead response

[a] You can define the number of AXI ID bits on this port using the AXISC_ID_BIT build parameter. If the ACP is implemented, [n] is [AXISC_ID_BIT:0], that is, the number of ACP ID bits + 1. If the ACP is not implemented, [n] is [4:0].


Table A.17 shows the AXI peripheral port write address signals.

Table A.17. AXI peripheral port write address signals

NameTypeSource/destinationDescription
AWVALIDMPOutputAXI3 deviceAddress valid.
AWREADYMPInputAddress ready.
AWIDMP[n][a]OutputAddress ID.
AWADDRMP[31:0]OutputAddress.
AWSIZEMP[1:0]OutputBurst size.
AWLENMP[3:0]OutputBurst length.
AWBURSTMP[1:0]OutputBurst type.
AWCACHEMP[3:0]OutputCache type.
AWPROTMP[2:0]OutputProtection type.
AWLOCKMP[1:0]OutputLock type.
AWUSERMP[10:0]OutputTransfer attributes. See AXI3 USER bits.

[a] You can define the number of AXI ID bits on this port using the AXISC_ID_BIT build parameter. If the ACP is implemented, [n] is [AXISC_ID_BIT:0], that is, the number of ACP ID bits + 1. If the ACP is not implemented, [n] is [4:0].


Table A.18 shows the AXI peripheral port write data signals.

Table A.18. AXI peripheral port write data signals

NameTypeSource/destinationDescription
WVALIDMPOutputAXI3 deviceWrite valid.
WREADYMPInputWrite ready.
WIDMP[n][a]OutputWrite ID.
WLASTMPOutputWrite last.
WSTRBMP[3:0]OutputWrite strobes.
WDATAMP[31:0]OutputWrite data.
WUSERMP[1:0]OutputTransfer attributes. See AXI3 USER bits.

[a] You can define the number of AXI ID bits on this port using the AXISC_ID_BIT build parameter. If the ACP is implemented, [n] is [AXISC_ID_BIT:0], that is, the number of ACP ID bits + 1. If the ACP is not implemented, [n] is [4:0].


Table A.19 shows the AXI peripheral port write response signals.

Table A.19. AXI peripheral port write response signals

NameTypeSource/destinationDescription
BVALIDMPInputAXI3 deviceResponse valid
BREADYMPOutputResponse ready
BIDMP[n][a]InputResponse ID
BRESPMP[1:0]InputWrite response

[a] You can define the number of AXI ID bits on this port using the AXISC_ID_BIT build parameter. If the ACP is implemented, [n] is [AXISC_ID_BIT:0], that is, the number of ACP ID bits + 1. If the ACP is not implemented, [n] is [4:0].


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