Appendix C. Revisions

This appendix describes the technical changes between released issues of this book.

Table C.1. Issue A

First release--

Table C.2. Differences between issue A and issue B


Updated the following terminology to conform to the ARM Architecture Reference Manual:

  • Precise abort changed to synchronous abort.

  • Imprecise abort changed to asynchronous abort.

  • Internal monitor changed to local monitor.

  • External monitor changed to global monitor.

Throughout book.All revisions
Added Debug and GIC architecture.ComplianceAll revisions
Added CTM interface.InterfacesAll revisions
Updated block diagram.Figure 2.1All revisions
Updated PMU architecture version.Debug and TraceAll revisions
Updated description of CLK.CLKAll revisions
Updated description of WFI and WFE standby modes.Standby modes and Standby mode with RAM retention All revisions
Updated description of individual processor debug reset.Individual processor debug resetAll revisions
Added timing diagram for powerdown and powerup sequence.Dormant modeAll revisions
Updated description of AXI master port 1.AXI master port 1All revisions
Updated description of AXI peripheral port.AXI peripheral port All revisions
Updated description of AXI TCM slave port.AXI TCM slave portAll revisions
Updated reset value for MIDR.Table 4.2 and Table 4.10r0p1
Updated reset value for CTR.Table 4.2, Table 4.10, Table 10.3, and Table 10.10All revisions
Updated reset value for DTCMRR and ITCMRR.Table 4.7 and Table 4.14All revisions
Updated description of CL 1 bits.Table 4.23All revisions
Updated description of bits[31,14].Table 4.25All revisions
Updated description of bits[31:30].Table 4.27All revisions
Deleted reference to Physical Address Register.Chapter 4 System ControlAll revisions
Changed DTCMR to DTCMRR and ITCMR to ITCMRR.Chapter 4 System ControlAll revisions
Separated DEER0-2 and IEER0-2 to show different bit assignment values.Table 4.39 and Table 4.40All revisions
Updated description of bits[31:28].Table 4.39 and Table 4.40All revisions
Updated usage of the Cache and TCM Debug Operation Register.Using the CTDORAll revisions
Updated version and reset value of FPSID.Table 5.2 and Table 5.4All revisions
Updated description of L1 memory system.About the L1 memory systemAll revisions
Moved description of data cache policy from Introduction chapter.Data cache policyAll revisions
Updated description of external faults.External faultsAll revisions
Updated cache disable and enable sequences.Cache interaction with memory systemAll revisions
Updated description of memory types and their behavior.Memory types and L1 memory system behaviorAll revisions
Updated bit allocations for Instruction tag RAM and SCU tag.Table 7.1All revisions
Updated RAM protection descriptions.Table 7.1All revisions
Updated RAM configuration values.Table 7.3All revisions
Deleted GPER and BPER from list of registers used in ECC.Processor registersAll revisions
Updated note about ECC on the ACP bus.ECC on external AXI busAll revisions
Updated description of lock-step.Lock-stepAll revisions
Updated description of split/lock.Static split/lockAll revisions
Deleted default memory map table. This information is covered in the ARM Architecture Reference Manual.Memory Protection UnitAll revisions
Updated description of low latency interrupt mode.Low latency interrupt modeAll revisions
Updated description of SCU registers.SCU registersAll revisions
Deleted reference to footnote for registers at offsets 0x70 and 0x74.Table 9.2All revisions
Clarified description of interrupt controller clock frequency.Interrupt controller clock frequencyAll revisions
Clarified description of legacy nFIQ input.Interrupt distributor interrupt sourcesAll revisions
Deleted reference to Secure accesses.Table 9.18All revisions
Added text about unpredictable accesses.

Distributor register descriptions

Interrupt interface register descriptions

Private timer and watchdog registers

Global Timer Counter Registers

All revisions
Updated reset value of ICCBPR.Table 9.23All revisions
Updated description of WDRESETREQ.Watchdog Counter RegisterAll revisions
Deleted reference to integration test registers.Chapter 10 Monitoring, Trace, and DebugAll revisions
Deleted reference to CP14 interface access.PMU management registersAll revisions
Updated description of processor events.Table 10.7All revisions
Updated description of debug registers.Debug register descriptionsAll revisions
Removed reference to CP14 access to processor ID registers.Table 10.8All revisions
Deleted description of breakpoint and watchpoint registers. This information is covered in the ARM Architecture Reference Manual.Breakpoint and Watchpoint Registers, DBGBVRn, DBGBCRn, DBGWVRn, and DBGWCRnAll revisions
Updated access type of ITCTRL.Debug management registersAll revisions
Updated description of processor ID registers.Processor ID RegistersAll revisions
Updated description of debug registers.Debug register descriptionsAll revisions
Added description of trigger inputs and outputs for CTI.Trigger inputs and outputsAll revisions

Added AXI3 master interface attributes.

About the L2 interfaceAll revisions

Updated supported AXI3 transfers.

Supported AXI3 transfersAll revisions

Updated descriptions for the following:





  • WUSERM0 and WUSERM1.

AXI3 USER bitsAll revisions

Updated TCM sizes.

Accessing RAMs using the AXI3 interfaceAll revisions
Updated all signals to match RTL.Appendix A Signal DescriptionsAll revisions
Updated description of nFIQOUT[N:0] and nIRQOUT[N:0].Table A.3All revisions
Updated description of SMPnAMP[N:0].Table A.4All revisions
Updated description of INCLKENMx and OUTCLKENMx.Table A.8All revisions
Updated description of ARLENMx[3:0].Table A.9All revisions
Updated description of AWLENMx[3:0].Table A.11All revisions

Updated descriptions of the following signals:

  • DBGACK[N:0].




Table A.46All revisions
Added CTI signals.Table A.52All revisions
Added power gating interface signals.Table A.54All revisions
Added appendix for instruction cycle timing.Appendix B Cycle Timings and Interlock BehaviorAll revisions

Table C.3. Differences between issue B and issue C

Updated the role of COMPENABLERedundant processor comparisonAll revisions
Updated the information about TCM RAMTest featuresAll revisions
Updated the description of the reset sequenceCortex-R7 MPCore powerup resetAll revisions
Updated the information about architectural registers after resetInitializationAll revisions
Updated description of exiting from WFE modeWait for EventAll revisions
Added information about access from the DTCMAbout the L1 memory systemAll revisions
Added information about multiple-bit errorsProtection methodAll revisions
Updated sectionLow latency interrupt modeAll revisions
Added caution about slave being private to the processorSystem configurability and QoSAll revisions
Updated the information about storageInstruction and data TCMAll revisions
Updated the information about PFILTERSTART and PFILTERENDSCU registersAll revisions
Updated the usage constraintsSCU CPU Power Status RegisterAll revisions
Updated the reset value of the ICDIIDR and the range of subsequent registersTable 9.17All revisions
Corrected the register name from ICDIPTRn to ICDIPRnTable 9.17All revisions
Updated the information about the ICDIPRn and the ICCPMRAll revisions
Updated the field valuesTable 9.20All revisions
Added information about comparator registersGlobal timerAll revisions
Updated the description of events 0x96-0x99Table 10.7All revisions
Updated information about read issuing capabilityTable 11.1All revisions
Updated sectionACP limitationsAll revisions
Updated the description of ARLENMxTable A.9All revisions
Updated the information about RDATAMPTable A.16All revisions
Updated description of ACLKENSCTable A.20All revisions
Updated description of RCTLPTYMxTable A.36All revisions
Updated directionality of signalsAll revisions
Updated width of RDATAERRCODEMTable A.36All revisions
Updated width of WDATAERRCODEMPTable A.37All revisions
Updated width of RDATAERRCODESCTable A.38All revisions
Changed signal name from AWREADPTYM0/M1/MP/SC to AWREADYPTYM0/M1/MP/SCAll revisions

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