8.2.3. Region attributes

Each region has a number of attributes associated with it. These control how a memory access is performed when the processor accesses an address that falls within a given region. The attributes are:

The Region Access Control Registers use five bits to encode the memory region type. These are the TEX[2:0], C, and B bits. Table 8.2 shows the mapping of these bits to memory region attributes.

Note

In earlier versions of the architecture, the TEX, C, and B bits were known as the Type Extension, Cacheable and Bufferable bits. These names no longer adequately describe the function of the B, C, and TEX bits.

In addition, the MPU Region Access Control Registers contain the shareable bit, S. This bit usually determines whether the memory region is Shareable (1) or Non-shareable (0). However, in some cases, the shareable attribute is forced by other attributes, for example, Strongly Ordered memory types are always Shareable.

Table 8.2. TEX[2:0], C, and B encodings

TEX[2:0]CBDescriptionMemory typeShareable?
00000Strongly Ordered.Strongly OrderedShareable
00001Shareable Device.DeviceShareable
00010Reserved.--
00100Outer and Inner Non-cacheable.NormalS bit[a]
00101Reserved.--
00110
00111Outer and Inner write-back, write-allocate.NormalS bit[a]
01000Non-shareable Device.DeviceNon-shareable
01001Reserved.--
0101X
011XX
1BBAA

Cacheable memory:

AA[b]

Inner policy.

BB[b]

Outer policy.

Normal

S bit[a]

[a] Region is Shareable if S == 1, and Non-shareable if S == 0.

[b] Table 8.3 shows the encoding for these bits.


Cacheable memory policies

When TEX[2] == 1, the memory region is cacheable memory, and the rest of the encoding defines the Inner and Outer cache policies:

TEX[1:0]

Defines the Outer cache policy.

C,B

Defines the Inner cache policy.

The same encoding is used for the Outer and Inner cache policies. Table 8.3 shows the encoding.

Table 8.3. Inner and Outer cache policy encoding

Memory attribute encodingCache policy
00Non-cacheable
01Write-back, write-allocate
10Reserved

When the processor performs a memory access through its AXI3 bus master interface:

  • The Inner attributes are indicated on the A*USERM signals.

  • The Outer attributes are indicated on the A*CACHEM signals.

For more information on region attributes, see the ARM® Architecture Reference Manual ARMv7-A and ARMv7-R edition.

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