11.4. STRT instructions

Take particular care with non-cacheable write accesses when using the STRT instruction. To put the correct information on the external bus ensure one of the following:

Table 11.13 shows Cortex-R7 processor modes and corresponding AxPROT values.

Table 11.13. Cortex-R7 processor mode and AxPROT values

Processor modeType of accessValue of AxPROT
UserCacheable read accessUser
PrivilegedPrivileged
UserNon-cacheable read accessUser
PrivilegedPrivileged
-Cacheable write accessAlways marked as Privileged
UserNon-cacheable write accessUser
PrivilegedNon-cacheable write access

Privileged, except when using STRT


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