5.5.3. Floating-Point Exception Register

The FPEXC Register characteristics are:

Purpose

Provides global enable control of the Advanced SIMD and VFP extensions.

Usage constraints

Accessible in all FPU configurations, with restrictions. See Processor modes for accessing the FPU system registers.

Configurations

Available in all FPU configurations.

Attributes

See the register summary in Table 5.2.

Figure 5.3 shows the FPEXC Register bit assignments.

Figure 5.3. FPEXC Register bit assignments

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Table 5.6 shows the FPEXC Register bit assignments.

Table 5.6. FPEXC Register bit assignments 

Bits

Name

Function

[31]

EX

Exception bit:

This bit reads-as-zero and ignores writes.

The Cortex-R7 FPU never requires asynchronous exception handling.

[30]

EN

Enable bit:

0b0

VFP extension is disabled.

0b1

VFP extension is enabled and operates normally.

The EN bit is cleared to 0 at reset.

[29]DEX[a]

Defined synchronous instruction exceptional flag:

0b0

No exception has occurred.

0b1

Attempt to perform a VFP vector operation has been trapped[b]

The DEX bit is cleared to 0 at reset.

[28:26]-RAZ/WI.
[25:0]-UNK/SBZP.

[a] In single-precision only configurations, this bit is not set for any double-precision operations, regardless of whether they are vector operations or not.

[b] The Cortex-R7 FPU hardware does not support the deprecated VFP short vector feature. Attempts to execute VFP data-processing instructions when the FPSCR.LEN field is non-zero result in the FPSCR.DEX bit being set and a synchronous Undefined instruction exception being taken. You can use software to emulate the short vector feature, if required.


You can access the FPEXC Register with the following VMSR instructions:

VMRS <Rd>, FPEXC ; Read Floating-Point Exception Register
VMSR FPEXC, <Rt> ; Write Floating-Point Exception Register
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