11.1. About the L2 interface

The Cortex-R7 L2 interface consists of one or two 64-bit wide AXI3 bus masters:

Table 11.1 shows the AXI3 master 0 and master 1 interface attributes.

Table 11.1. AXI3 master 0 and master 1 interface attributes

AttributeFormat
Write issuing capability

29 for an implementation with one processor, including:

  • 15 ACP writes.

  • Eight noncacheable writes.

  • Four evictions.

  • Two DDI evictions.

41 for an implementation with two processors, including:

  • 15 ACP writes.

  • For each processor:

    • Eight noncacheable writes.

    • Four evictions.

  • Two DDI evictions.

Read issuing capability

31 for an implementation with one processor, including:

  • 15 ACP reads.

  • Four data side linefill reads.

  • Eight instruction side linefill reads.

  • Four noncacheable reads.

47 for an implementation with two processors, including:

  • 15 ACP reads.

  • For each processor:

    • Four data side linefill reads.

    • Eight instruction side linefill reads.

    • Four noncacheable reads.

Combined issuing capability88
Write interleave capability1

Note

The numbers in Table 11.1 are the theoretical maximums for the Cortex-R7 MPCore processor. A typical system is unlikely to reach these numbers. ARM recommends that you perform profiling to tailor your system resources appropriately for optimum performance.

The AXI3 protocol and meaning of each AXI3 signal are not described in this document. For more information see the AMBA AXI Protocol Specification.

The following sections describe the Cortex-R7 L2 interface:

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