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Home > Floating Point Unit Programmers Model > Register descriptions > Floating-Point Status and Control Register |
The FPSCR characteristics are:
Provides user-level control of the FPU.
There are no usage constraints.
Available in all FPU configurations.
See the register summary in Table 5.2.
Figure 5.2 shows the FPSCR bit assignments.
Table 5.5 shows the FPSCR bit assignments.
Table 5.5. FPSCR bit assignments
Bits | Name | Function |
---|---|---|
[31] | N | Set to 1 if a comparison operation produces a less than result. |
[30] | Z | Set to 1 if a comparison operation produces an equal result. |
[29] | C | Set to 1 if a comparison operation produces an equal, greater than, or unordered result. |
[28] | V | Set to 1 if a comparison operation produces an unordered result. |
[27] | - | UNK/SBZP. |
[26] | AHP | Alternative half-precision control bit:
|
[25] | DN | Default NaN mode control bit:
Advanced SIMD arithmetic always uses the Default NaN setting, regardless of the value of the DN bit. |
[24] | FZ | Flush-to-zero mode control bit:
Advanced SIMD arithmetic always uses the Flush-to-zero setting, regardless of the value of the FZ bit. |
[23:22] | RMode | Rounding Mode control field:
Advanced SIMD arithmetic always uses the Round to nearest setting, regardless of the value of the RMode bits. |
[21:20] | Stride | Stride control used for backwards compatibility with short vector values. See the ARM® Architecture Reference Manual ARMv7-A and ARMv7-R edition. |
[19] | - | UNK/SBZP. |
[18:16] | Len | Vector length, used for backwards compatibility with short vector values. See the ARM® Architecture Reference Manual ARMv7-A and ARMv7-R edition. |
[15:8] | - | UNK/SBZP. |
[7] | IDC | Input Denormal cumulative exception flag.[a] |
[6:5] | - | UNK/SBZP. |
[4] | IXC | Inexact cumulative exception flag.a |
[3] | UFC | Underflow cumulative exception flag.a |
[2] | OFC | Overflow cumulative exception flag.a |
[1] | DZC | Division by Zero cumulative exception flag.a |
[0] | IOC | Invalid Operation cumulative exception flag.a |
[a] The exception flags, bit [7] and bits [4:0] of the FPSCR are exported on the FPUFLAGS output so they can be monitored externally to the processor, if required. |
You can access the FPSCR with the following VMSR
instructions:
VMRS <Rd>, FPSCR ; Read Floating-Point Status and Control Register
VMSR FPSCR, <Rt> ; Write Floating-Point Status and Control Register