6.4.2. Cache error detection and correction

The processor can detect, handle, report, and correct cache memory errors. This section describes:

Error build options

The caches can detect and correct errors depending on the build options used in the implementation. If the ECC build option is enabled:

  • The instruction cache is protected by a 64-bit ECC scheme. The data RAMs include eight bits of ECC code for every 64 bits of data. The tag RAMs include seven bits of ECC code to cover the tag and valid bit.

  • The data cache is protected by a 32-bit ECC scheme. The data RAMs include seven bits of ECC code for every 32 bits of data. The tag RAMs include seven bits of ECC code to cover the tag and control bits.

Address decoder faults

The error detection schemes described in this section provide protection against errors that occur in the data stored in the cache RAMs. Each RAM normally includes a decoder that enables access to that data and, if an error occurs in this logic, it is not normally detected by these error detection schemes. The processor includes features that enable it to detect some address decoder faults.

Handling cache ECC errors

Table 6.2 shows the behavior of the processor on a cache ECC error, depending on bit[9] of the ACTLR.

Table 6.2. Cache ECC error behavior

BitBehavior
[9]ECC on.

See Disabling or enabling error checking for information on how to safely change these bits.

When ECC checking is enabled, hardware recovery is always enabled. When an ECC error is detected, the processor tries to evict the cache line containing the error. If the line is clean, it is invalidated, and the correct data is reloaded from the L2 memory system. If the line is dirty, the eviction writes the dirty data out to the L2 memory system, and in the process it corrects any 1-bit errors. The corrected data is then reloaded from the L2 memory system.

If a 2-bit error is detected in data ram for a dirty line or in tag RAM, the error is not correctable. If the 2-bit error is in the tag RAM, no data is written to the L2 memory system. If the 2-bit error is in the data RAM, the cache line is written to the L2 memory system, but the AXI master port WSTRBM signal is LOW for the data that contains the error. If an uncorrectable error is detected, an ECC primary output is always generated because data might have been lost. It is expected that such a situation can be fatal to the software process running.

Errors on instruction cache read

All ECC errors detected on instruction cache reads are correctable.

All detectable errors in the instruction cache can always be recovered from because the instruction cache never contains dirty data.

Errors on evictions

If the cache controller has determined a cache miss has occurred, it might have to do an eviction before a linefill can take place. This can occur on reads and writes. Certain cache maintenance operations also generate evictions. If it is a data-cache line that is dirty, an ECC error might be detected on the line being evicted:

  • If the error is correctable, it is corrected inline before the data is written to the external memory using the L2 memory interface.

  • If there is an uncorrectable error in the tag RAM, the write is not done.

  • If there is an uncorrectable error in the data RAM, the AXI master port WSTRBM signal is deasserted for the word(s) with an error.

Errors on cache maintenance operations

The following sections describe errors on cache maintenance operations:

Invalidate all instruction cache

This operation does not generate any errors.

Invalidate instruction cache by address

This operation requires a cache lookup. Any errors found in the set that was looked up are fixed by invalidating that line and, if the address in question is found in the set, it is invalidated.

Any detected error is signaled with the appropriate event.

Invalidate data cache by address

This operation requires a cache lookup. Any correctable errors found in the set that was looked up are fixed and, if the address in question is found in the set, it is invalidated.

Any detected error is signaled with the appropriate event.

Invalidate data cache by set/way

This operation does not require a cache lookup. It refers to a particular cache line.

Clean data cache by address

This operation requires a cache lookup. Any correctable errors found in the set that was looked up are fixed and, if the address in question is found in the set, the instruction carries on with the clean operation.

If the tag RAM has an uncorrectable error, the data is not written to memory.

If the line is dirty, the data is written back to external memory. If the data has an uncorrectable error, the words with the error have their WSTRBM AXI signal deasserted. If there is a correctable error, the line has the error corrected inline before it is written back to memory.

Any detected error is signaled with the appropriate event.

Clean data cache by set/way

This operation does not require a cache lookup. It refers to a particular cache line.

The tag RAMs for the cache line are checked.

If the tag RAM has an uncorrectable error, the data is not written to memory.

If the line is dirty, the data is written back to external memory. If the data has an uncorrectable error, the words with the error have their WSTRBM AXI signal deasserted. If there is a correctable error, the line has the error corrected inline before it is written back to memory.

Any detected error is signaled with the appropriate event.

Clean and invalidate data cache by address

This operation requires a cache lookup. Any correctable errors found in the set that was looked up are fixed and, if the address in question is found in the set, the instruction carries on with the clean and invalidate operation.

If the tag RAM has an uncorrectable error, the data is not written to memory.

If the line is dirty, the data is written back to external memory. If the data has an uncorrectable error, the words with the error have their WSTRBM AXI signal deasserted. If there is a correctable error, the line has the error corrected inline before it is written back to memory.

Any detected error is signaled with the appropriate event.

Clean and invalidate data cache by set/way

This operation does not require a cache lookup. It refers to a particular cache line.

The tag RAMs for the cache line are checked.

If the tag RAM has an uncorrectable error, the data is not written to memory.

If the line is dirty, the data is written back to external memory. If the data has an uncorrectable error, the words with the error have their WSTRBM AXI signal deasserted. If there is a correctable error, the line has the error corrected inline before it is written back to memory.

Any detected error is signaled with the appropriate event.

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