6.4.4. Cache interaction with memory system

This section describes how to enable or disable the cache RAMs, and to enable or disable error checking. After you enable or disable the instruction cache, you must issue an ISB instruction to flush the pipeline. This ensures that all subsequent instruction fetches see the effect of enabling or disabling the instruction cache.

After reset, you must invalidate each cache before enabling it.

When disabling the data cache, you must clean the entire cache to ensure that any dirty data is flushed to L2 memory.

Before enabling the data cache, you must invalidate the entire data cache if L2 memory might have changed since the cache was disabled.

Before enabling the instruction cache, you must invalidate the entire instruction cache if L2 memory might have changed since the cache was disabled.

Disabling or enabling instruction cache

The following code is an example of enabling the instruction cache:

MRC p15, 0, R1, c1, c0, 0  ; Read System Control Register configuration data
ORR R1, R1, #0x1 <<12      ; instruction cache enable
MCR p15, 0, r0, c7, c5, 0  ; Invalidate entire instruction cache
MCR p15, 0, R1, c1, c0, 0  ; enabled instruction cache
ISB

The following code is an example of disabling the instruction cache:

MRC p15, 0, R1, c1, c0, 0   ; Read System Control Register configuration data
BIC R1, R1, #0x1 <<12       ; instruction cache enable
MCR p15, 0, R1, c1, c0, 0   ; disabled instruction cache
ISB

Disabling or enabling data cache

The following code is an example of enabling the data cache:

MRC p15, 0, R1, c1, c0, 0  ; Read System Control Register configuration data
ORR R1, R1, #0x1 <<2
DSB
; Invalidate the data cache with a loop of invalidate by set/way operations. This routine will depend on the data cache size.
MCR p15, 0, R1, c1, c0, 0  ; enabled data cache

The following code is an example of disabling the cache RAMs:

MRC p15, 0, R1, c1, c0, 0  ; Read System Control Register configuration data
BIC R1, R1, #0x1 <<2
DSB
MCR p15, 0, R1, c1, c0, 0  ; disabled data cache
; Clean entire data cache. This routine will depend on the data cache size.

Disabling or enabling error checking

The following code is the recommended sequence to perform the change:

MRC p15, 0, r0, c1, c0, 0  ; Read System Control Register
BIC r0, r0, #0x1 << 2      ; Disable data cache bit
BIC r0, r0, #0x1 << 12     ; Disable instruction cache bit
DSB
MCR p15, 0, r0, c1, c0, 0  ; Write System Control Register
ISB ; Ensures following instructions are not executed from cache
; Clean entire data cache. This routine will depend on the data cache size. It can be omitted if the cache has not been enabled yet.
MRC p15, 0, r1, c1, c0, 1  ; Read Auxiliary Control Register
; Change bits 10:9 as needed
MCR p15, 0, r1, c1, c0, 1  ; Write Auxiliary Control Register
; Invalidate the data cache. This routine will depend on the data cache size
MCR p15, 0, r0, c7, c5, 0  ; Invalidate entire instruction cache
MRC p15, 0, r0, c1, c0, 0  ; Read System Control Register
ORR r0, r0, #0x1 << 2      ; Enable data cache bit
ORR r0, r0, #0x1 << 12     ; Enable instruction cache bit
DSB
MCR p15, 0, r0, c1, c0, 0  ; Write System Control Register
ISB
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