8.2.4. MPU interaction with memory system

This section describes how to enable and disable the MPU. After you enable or disable the MPU, the pipeline must be flushed using ISB and DSB instructions to ensure that all subsequent instruction fetches see the effect of turning on or off the MPU.

Before you enable or disable the MPU you must:

  1. Program all relevant CP15 registers. This includes setting up at least one memory region that covers the currently executing code, and that provides read and execute permissions in at least privileged mode.

  2. Invalidate the instruction cache.

  3. Enable the instruction cache.

  4. Invalidate the data cache.

The following code is an example of enabling the MPU:

MRC p15, 0, R1, c1, c0, 0    ; read CP15 register 1
ORR R1, R1, #0x1
DSB
MCR p15, 0, R1, c1, c0, 0    ; enable MPU
ISB
Fetch from programmed memory map
Fetch from programmed memory map
Fetch from programmed memory map
Fetch from programmed memory map

The following code is an example of disabling the MPU:

MRC p15, 0, R1, c1, c0, 0    ; read CP15 register 1
BIC R1, R1, #0x1
DSB
MCR p15, 0, R1, c1, c0, 0    ; disable MPU 
ISB
Fetch from default memory map
Fetch from default memory map
Fetch from default memory map
Fetch from default memory map

The MPU does not check accesses from the AXI TCM slave. You can configure the processor to enable access to the TCM interfaces from the AXI TCM slave port.

For more information on the default memory map, see the ARM® Architecture Reference Manual ARMv7-A and ARMv7-R edition.

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