9.5.2. Private timer and watchdog registers

Addresses are relative to the base address of the timer and watchdog region defined by the private memory map. See Private memory region. All timer and watchdog registers are word-accessible only. Any other access is unpredictable

Use nPERIPHRESET to reset these registers, except for the Watchdog Reset Status Register.

nWDRESET resets the Watchdog Reset Status Register. See Private memory region and Reset signals.

Table 9.25 shows the timer and watchdog registers. All registers not described in Table 9.25 are Reserved.

Table 9.25. Timer and watchdog registers 


Note

The private timers stop counting when the associated processor is in debug state.

Private Timer Load Register

The Timer Load Register contains the value copied to the Timer Counter Register when it decrements down to zero with auto-reload mode enabled. Writing to the Timer Load Register means that you also write to the Timer Counter Register.

Private Timer Counter Register

The Timer Counter Register is a decrementing counter.

The Timer Counter Register decrements if the timer is enabled using the timer enable bit in the Timer Control Register. If a Cortex-R7 processor timer is in debug state, the counter only decrements when the processor returns to non-debug state.

When the Timer Counter Register reaches zero and auto-reload mode is enabled, it reloads the value in the Timer Load Register and then decrements from that value. If auto-reload mode is not enabled, the Timer Counter Register decrements down to zero and stops.

When the Timer Counter Register reaches zero, the timer interrupt status event flag is set and the interrupt ID 29 is set as pending in the Interrupt Distributor, if interrupt generation is enabled in the Timer Control Register.

Writing to the Timer Counter Register or Timer Load Register forces the Timer Counter Register to decrement from the newly written value.

Private Timer Control Register

Figure 9.23 shows the Private Timer Control Register bit assignments.

Figure 9.23. Private Timer Control Register bit assignments

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Table 9.26 shows the Private Timer Control Register bit assignments.

Table 9.26. Private Timer Control Register bit assignments 

BitsNameFunction
[31:16]-UNK/SBZP.
[15:8]Prescaler

The prescaler modifies the clock period for the decrementing event for the Counter Register. See Calculating timer intervals for the equation.

[7:3]-UNK/SBZP.
[2]IRQ enable

If set, the interrupt ID 29 is set as pending in the Interrupt Distributor when the event flag is set in the Timer Status Register.

[1]Auto-reload

Auto-reload enable:

0

Single-shot mode. Counter decrements down to zero, sets the event flag and stops.

1

Auto-reload mode. Each time the Counter Register reaches zero, it is reloaded with the value contained in the Timer Load Register.

[0]Timer enable

Timer enable:

0

Timer is disabled and the counter does not decrement. All registers can still be read and written.

1

Timer is enabled and the counter decrements normally.


The timer is incremented every prescaler value plus 1. For example, if the prescaler has a value of five, the global timer is incremented every six clock cycles. PERIPHCLK is the reference clock for this.

Private Timer Interrupt Status Register

Figure 9.24 shows the Private Timer Interrupt Status Register bit assignments.

This is a banked register for all Cortex-R7 processors present.

The event flag is a sticky bit that is automatically set when the Counter Register reaches zero. If the timer interrupt is enabled, Interrupt ID 29 is set as pending in the Interrupt Distributor after the event flag is set. The event flag is cleared by writing a 1 to bit[0].

Figure 9.24. Private Timer Interrupt Status Register bit assignments

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Watchdog Load Register

The Watchdog Load Register contains the value copied to the Watchdog Counter Register when it decrements down to zero with auto-reload mode enabled, in Timer mode. Writing to the Watchdog Load Register means that you also write to the Watchdog Counter Register.

Watchdog Counter Register

The Watchdog Counter Register is a decrementing counter.

It decrements if the Watchdog is enabled using the Watchdog enable bit in the Watchdog Control Register. If the Cortex-R7 processor associated with the Watchdog is in debug state, the counter does not decrement until the processor returns to non-debug state.

When the Watchdog Counter Register reaches zero and auto-reload mode is enabled, and in timer mode, it reloads the value in the Watchdog Load Register and then decrements from that value. If auto-reload mode is not enabled or the watchdog is not in timer mode, the Watchdog Counter Register decrements down to zero and stops.

When in watchdog mode the only way to update the Watchdog Counter Register is to write to the Watchdog Load Register. When in timer mode the Watchdog Counter Register is write accessible.

The behavior of the watchdog when the Watchdog Counter Register reaches zero depends on its current mode:

Timer mode

When the Watchdog Counter Register reaches zero, the watchdog interrupt status event flag is set. If interrupt generation is enabled in the Watchdog Control Register, interrupt ID 30 is set as pending in the Interrupt Distributor.

Watchdog mode

If a software failure prevents the Watchdog Counter Register from being refreshed:

  • The Watchdog Counter Register reaches zero.

  • The Watchdog reset status flag is set.

  • The associated WDRESETREQ reset request output is asserted. WDRESETREQ is valid for one PERIPHCLK cycle.

The external reset source is then responsible for resetting all or part of the Cortex-R7 MPCore processor design.

Watchdog Control Register

Figure 9.25 shows the Watchdog Control Register bit assignments.

Figure 9.25. Watchdog Control Register bit assignments

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Table 9.27 shows the Watchdog Control Register bit assignments.

Table 9.27. Watchdog Control Register bit assignments 

BitsNameFunction
[31:16]-

Reserved.

[15:8]Prescaler

The prescaler modifies the clock period for the decrementing event for the Counter Register. See Calculating timer intervals.

[7:4]-

Reserved.

[3]Watchdog mode

Watchdog mode enable:

0

Timer mode. This is the default. Writing a zero to this bit has no effect. You must use the Watchdog Disable Register to put the watchdog into timer mode. See Watchdog Disable Register.

1

Watchdog mode.

[2]IT Enable

If set, the interrupt ID 30 is set as pending in the Interrupt Distributor when the event flag is set in the watchdog Status Register.

In watchdog mode this bit is ignored.

[1]Auto-reload

Auto-reload enable:

0

Single-shot mode. Counter decrements down to zero, sets the event flag and stops.

1

Auto-reload mode. Each time the Counter Register reaches zero, it is reloaded with the value contained in the Load Register and then continues decrementing.

[0]Watchdog Enable

Global watchdog enable:

0

Watchdog is disabled and the counter does not decrement. All registers can still be read or written.

1

Watchdog is enabled and the counter decrements normally.


Watchdog Interrupt Status Register

Figure 9.26 shows the Watchdog Interrupt Status Register bit assignments.

Figure 9.26. Watchdog Interrupt Status Register bit assignments

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The event flag is a sticky bit that is automatically set when the Counter Register reaches zero in timer mode. If the watchdog interrupt is enabled, Interrupt ID 30 is set as pending in the Interrupt Distributor after the event flag is set. The event flag is cleared when written with a value of 1. Trying to write a zero to the event flag or a one when it is not set has no effect.

Watchdog Reset Status Register

Figure 9.27 shows the Watchdog Reset Status Register bit assignments.

Figure 9.27. Watchdog Reset Status Register bit assignments

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In watchdog mode, the reset flag is a sticky bit that is automatically set when the Counter Register reaches zero and a reset request is sent accordingly.

For lock-step or split/lock in lock-step mode, the reset must not be applied immediately to the entire Cortex-R7 MPCore. This is because after reset the sticky flag is set in one processor but not the other and this leads to the assertion of COMPFAULT. Therefore, if one processor has its watchdog flag set, the other processor must reach the same state, that is, also having its watchdog flag set.

The reset flag is cleared when written with a value of 1. Trying to write a zero to the reset flag or a one when it is not set has no effect. This flag is not reset by normal Cortex-R7 processor resets but has its own reset line, nWDRESET. nWDRESET must not be asserted when the processor reset assertion is the result of a watchdog reset request with WDRESETREQ. This distinction enables software to differentiate between a normal boot sequence, reset flag is zero, and one caused by a previous watchdog time-out, reset flag set to one.

Watchdog Disable Register

Use the Watchdog Disable Register to switch from watchdog to timer mode. The software must write 0x12345678 then 0x87654321 successively to the Watchdog Disable Register so that the watchdog mode bit in the Watchdog Control Register is set to zero.

If one of the values written to the Watchdog Disable Register is incorrect or if any other write occurs in between the two word writes, the watchdog remains in its current state. To reactivate the Watchdog, the software must write 1 to the watchdog mode bit of the Watchdog Control Register. See Watchdog Control Register.

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