2.1.1. Components of the Cortex-R7 MPCore processor

The main components of the Cortex-R7 MPCore processor are:

L1 memory system

The L1 memory system has:

  • 64-bit data paths throughout the memory system.

  • Export of memory attributes for external memory systems.

  • Separate optional instruction and data caches each with a fixed line length of 32 bytes.

Snoop Control Unit

The SCU connects the Cortex-R7 processors to the memory system and peripherals through the AXI3 interfaces. The SCU has an optional AXI3 64-bit slave port, the Accelerator Coherency Port (ACP). See Accelerator Coherency Port.

See About multiprocessing and the SCU for more information.


The SCU supports L1 data cache coherency, but does not support hardware management of coherency of the instruction caches.

Interrupt controller

The interrupt controller provides support for handling multiple interrupt sources. See Interrupt controller for more information.


The Timers provide the ability to schedule events and trigger interrupts. See Private timer and watchdog and Global timer for more information.

Debug and Trace

The debug and trace logic includes:

  • Support for ARMv7 Debug architecture with an APB slave interface for access to the debug registers.

  • Performance Monitor Unit (PMU) based on the PMUv1 architecture.

  • Embedded Trace Macrocell (ETM) based on the ETMv4 architecture and dedicated ATB interfaces per processor.

  • Cross Trigger Interface (CTI) and Cross Trigger Matrix (CTM) for multi-processor debugging.

See the following for more information:


The Cortex-R7 MPCore processor can be configured so that it can be switched, under reset, between a twin-processor performance mode and a dual-redundant lock-step. This feature imposes extra constraints on the software usage model. ARM provides an init code sequence to guarantee the processor and the redundant processor leave reset in exactly the same state. See Static split/lock for more information.

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