4.2.9. System identification, control, and configuration register

Table 4.10 shows the system identification, control, and configuration registers.

Table 4.10. System identification, control, and configuration registers

NameCRnOp1CRmOp2Reset Description

MIDR

c00c000x410FC171

Main ID Register

CTR

10x8333C003

Cache Type Register, see the ARM® Architecture Reference Manual ARMv7-A and ARMv7-R edition

TCMTR2

Implementation dependent[a]

TCM Type Register, see the ARM® Architecture Reference Manual ARMv7-A and ARMv7-R edition

MPUIR4

Implementation dependent[b]

MPU Type Register
MPIDR5Implementation dependent[c]

Multiprocessor Affinity Register

REVIDR6Implementation dependent

Revision ID Register

ID_PFR0c100x00000131Processor Feature Register 0, see the ARM® Architecture Reference Manual ARMv7-A and ARMv7-R edition
ID_PFR110x00000001Processor Feature Register 1, see the ARM® Architecture Reference Manual ARMv7-A and ARMv7-R edition
ID_DFR020x00010404Debug Feature Register, see the ARM® Architecture Reference Manual ARMv7-A and ARMv7-R edition
ID_AFR030x00000000Auxiliary Feature Register 0, see the ARM® Architecture Reference Manual ARMv7-A and ARMv7-R edition
ID_MMFR040x00110130Memory Model Feature Register 0, see the ARM® Architecture Reference Manual ARMv7-A and ARMv7-R edition
ID_MMFR150x00000000Memory Model Feature Register 1, see the ARM® Architecture Reference Manual ARMv7-A and ARMv7-R edition
ID_MMFR260x01200000Memory Model Feature Register 2, see the ARM Architecture Reference Manual
ID_MMFR370x00002111Memory Model Feature Register 3, see the ARM® Architecture Reference Manual ARMv7-A and ARMv7-R edition
ID_ISAR0c200x02101111Instruction Set Attributes Register 0, see the ARM® Architecture Reference Manual ARMv7-A and ARMv7-R edition
ID_ISAR110x13112111Instruction Set Attributes Register 1, see the ARM® Architecture Reference Manual ARMv7-A and ARMv7-R edition
ID_ISAR220x21232141Instruction Set Attributes Register 2, see the ARM® Architecture Reference Manual ARMv7-A and ARMv7-R edition
ID_ISAR330x01112131Instruction Set Attributes Register 3, see the ARM® Architecture Reference Manual ARMv7-A and ARMv7-R edition
ID_ISAR440x00010142Instruction Set Attributes Register 4, see the ARM® Architecture Reference Manual ARMv7-A and ARMv7-R edition
CCSIDRc01c00UNK[d]Cache Size ID Register
CLIDR1

Implementation dependent[e]

Cache Level ID Register

AIDR

70x00000000Auxiliary ID Register
CSSELR2c00

Implementation dependent

Cache Size Selection Register

SCTLR

c10c00-

System Control Register

ACTLR10x00000000

Auxiliary Control Register

CPACR

20xC0000000

Coprocessor Access Control Register

[a] If TCMs are implemented 0x80010001.

If TCMs are not implemented 0x00000000.

[b] For 12 MPU regions 0x00000c00.

For 16 MPU regions 0x00001000.

[c] Dependent on external signal CLUSTERID and the number of configured processors in the Cortex-R7 MPCore processor.

[d] Dependent on cache sizes and whether cache is on or off.

[e] If cache present 0x09200003.

If cache not present 0x00000000.


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