4.2.12. Cache maintenance registers

Table 4.13 shows the cache maintenance registers.

Table 4.13. Cache maintenance registers

NameCRnOp1CRmOp2Reset Description
NOPc70c04-No operation, see the ARM® Architecture Reference Manual ARMv7-A and ARMv7-R edition
ICIALLUISc10-Invalidate all instruction caches to PoU Inner Shareable, see the ARM® Architecture Reference Manual ARMv7-A and ARMv7-R edition
BPIALLIS6-Invalidate entire branch predictor array Inner Shareable, see the ARM® Architecture Reference Manual ARMv7-A and ARMv7-R edition
ICIALLUc50-Invalidate entire instruction cache, see the ARM® Architecture Reference Manual ARMv7-A and ARMv7-R edition
ICIMVAU1-Invalidate instruction cache by VA to PoU, see the ARM® Architecture Reference Manual ARMv7-A and ARMv7-R edition
CP15ISB4-Instruction Synchronization Barrier operation, see the ARM® Architecture Reference Manual ARMv7-A and ARMv7-R edition
BPIALL6-Invalidate entire branch predictor array, see the ARM® Architecture Reference Manual ARMv7-A and ARMv7-R edition
BPIMVA -Invalidate MVA from branch predictors, see the ARM® Architecture Reference Manual ARMv7-A and ARMv7-R edition
DCIMVACc61-Invalidate data cache line by VA to PoC, see the ARM® Architecture Reference Manual ARMv7-A and ARMv7-R edition
DCISW2-Invalidate data cache line by Set/Way, see the ARM® Architecture Reference Manual ARMv7-A and ARMv7-R edition
DCCMVACc101-Clean data cache line to PoC by VA, see the ARM® Architecture Reference Manual ARMv7-A and ARMv7-R edition
DCCSW2-Clean data cache line by Set/Way. see the ARM® Architecture Reference Manual ARMv7-A and ARMv7-R edition
CP15DSBc104-Data Synchronization Barrier operation, see the ARM® Architecture Reference Manual ARMv7-A and ARMv7-R edition
CP15DMB5-Data Memory Barrier operation, see the ARM® Architecture Reference Manual ARMv7-A and ARMv7-R edition
DCCMVAUc111-Clean data or unified cache line by VA to PoU, see the ARM® Architecture Reference Manual ARMv7-A and ARMv7-R edition
DCCIMVACc141-Clean and invalidate data cache line by VA to PoC, see the ARM® Architecture Reference Manual ARMv7-A and ARMv7-R edition
DCCISW2-Clean and invalidate data cache line by Set/Way, see the ARM® Architecture Reference Manual ARMv7-A and ARMv7-R edition

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