4.2.14. Performance monitor registers

Table 4.15 shows the performance monitor registers.

Table 4.15. Performance monitor registers

NameCRnOp1CRmOp2Reset Description
PMCRc90c1200x41104000Performance Monitor Control Register, see the ARM® Architecture Reference Manual ARMv7-A and ARMv7-R edition
PMCNTENSET10x00000000Count Enable Set Register, see the ARM® Architecture Reference Manual ARMv7-A and ARMv7-R edition
PMCNTENCLR20x00000000Count Enable Clear Register, see the ARM® Architecture Reference Manual ARMv7-A and ARMv7-R edition
PMOVSR30x00000000Overflow Flag Status Register, see the ARM® Architecture Reference Manual ARMv7-A and ARMv7-R edition
PMSWINC4UNKSoftware Increment Register, see the ARM® Architecture Reference Manual ARMv7-A and ARMv7-R edition
PMSELR50x00000000Event Counter Selection Register, see the ARM® Architecture Reference Manual ARMv7-A and ARMv7-R edition
PMCCNTRc130UNKCycle Count Register, see the ARM® Architecture Reference Manual ARMv7-A and ARMv7-R edition
PMXEVTYPER1UNKEvent Selection Register, see the ARM® Architecture Reference Manual ARMv7-A and ARMv7-R edition
PMXEVCNTRc90c132UNKPerformance Monitor Count Registers, see the ARM® Architecture Reference Manual ARMv7-A and ARMv7-R edition
PMUSERENRc1400x00000000User Enable Register, see the ARM® Architecture Reference Manual ARMv7-A and ARMv7-R edition
PMINTENSET10x00000000Interrupt Enable Set Register, see the ARM® Architecture Reference Manual ARMv7-A and ARMv7-R edition
PMINTENCLR20x00000000Interrupt Enable Clear Register, see the ARM® Architecture Reference Manual ARMv7-A and ARMv7-R edition

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