4.2.16. Implementation-defined registers

Table 4.17 shows the implementation-defined registers.

Table 4.17. Implementation-defined registers

NameCRnOp1CRmOp2Reset Description
PCRc150c000x00000020Power Control Register
CTDORc10UNK

Cache and TCM Debug Operation Register

RADRLO1UNK

RAM Access Data Registers, bits[31:0]

RADRHI2UNK

RAM Access Data Registers, bits[63:32]

RAECCR[a]3UNK

RAM Access ECC Register

D_ECC_ENTRY_0[a]c20UNKECC Error Registers
D_ECC_ENTRY_1[a]1UNK
D_ECC_ENTRY_2[a]2UNK
I_ECC_ENTRY_0[a]c30UNK
I_ECC_ENTRY_1[a]1UNK
I_ECC_ENTRY_2[a]2UNK
DTCM_ECC_ENTRY[b]c40UNK
ITCM_ECC_ENTRY[b]c50UNK
CBAR4c00UNKConfiguration Base Address Register

[a] Only present if ECC is present, otherwise RAZ/WI.

[b] Only present if ECC and TCM are present, otherwise RAZ/WI.


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