7.4.1. Reporting errors

The ECC logic protecting the AXI buses assumes that an entity in the system other than the processor is responsible for reacting to any ECC error detected on the bus, to restart the system correctly or to take any related actions. For this reason, the following events are output for every protected AXI interface:


A correctable ECC error has been detected on read or write data.


A fatal ECC error has been detected on one of the channels.

It is also assumed that any signal of the bus always has a defined value after reset.

Copyright © 2012, 2014 ARM. All rights reserved.ARM DDI 0458C