ARM® Cortex®-R7 MPCore Technical Reference Manual

Revision: r0p1


Table of Contents

Preface
About this book
Product revision status
Intended audience
Using this book
Glossary
Conventions
Additional reading
Feedback
Feedback on this product
Feedback on content
1. Introduction
1.1. About the Cortex-R7 MPCore processor
1.2. Compliance
1.2.1. ARM architecture
1.2.2. Trace macrocell
1.2.3. Advanced Microcontroller Bus Architecture
1.2.4. Debug architecture
1.2.5. Generic Interrupt Controller architecture
1.3. Features
1.4. Interfaces
1.4.1. APB Debug interface
1.4.2. ETM/ATB interface
1.4.3. CTM interface
1.4.4. PMU interface
1.4.5. Test interface
1.5. Configurable options
1.6. Redundant processor comparison
1.6.1. Split/lock
1.7. Test features
1.8. Product documentation and design flow
1.8.1. Documentation
1.8.2. Design flow
1.9. Product revisions
2. Functional Description
2.1. About the functions
2.1.1. Components of the Cortex-R7 MPCore processor
2.2. Interfaces
2.2.1. AXI3 interface
2.2.2. Debug and PMU APB interface
2.2.3. ATB interface
2.2.4. DFT interface
2.2.5. MBIST controller interface
2.3. Clocking, resets, and initialization
2.3.1. Clocking
2.3.2. Resets
2.3.3. Initialization
2.4. Power management
2.4.1. Individual processor power management
2.4.2. Power domains
2.5. Processor ports
2.5.1. AXI master port 0
2.5.2. AXI master port 1
2.5.3. AXI peripheral port
2.5.4. AXI TCM slave port
2.5.5. Accelerator Coherency Port
2.5.6. Memory Reconstruction Port
2.5.7. Private memory region
3. Programmers Model
3.1. About the programmers model
3.2. The VFP extension
3.3. Multiprocessing extensions
3.4. Memory formats
3.5. Addresses in the Cortex-R7 MPCore processor
4. System Control
4.1. About system control
4.2. Register summary
4.2.1. c0 registers
4.2.2. c1 registers
4.2.3. c5 registers
4.2.4. c6 registers
4.2.5. c7 registers
4.2.6. c9 registers
4.2.7. c13 registers
4.2.8. c15 registers
4.2.9. System identification, control, and configuration register
4.2.10. Fault handling registers
4.2.11. MPU registers
4.2.12. Cache maintenance registers
4.2.13. Interface control and configuration registers
4.2.14. Performance monitor registers
4.2.15. Miscellaneous system control registers
4.2.16. Implementation-defined registers
4.3. Register descriptions
4.3.1. Main ID Register
4.3.2. MPU Type Register
4.3.3. Multiprocessor Affinity Register
4.3.4. Revision ID Register
4.3.5. Cache Size ID Register
4.3.6. Cache Level ID Register
4.3.7. Auxiliary ID Register
4.3.8. Cache Size Selection Register
4.3.9. System Control Register
4.3.10. Auxiliary Control Register
4.3.11. Coprocessor Access Control Register
4.3.12. MPU memory region programming registers
4.3.13. DTCM Region Register
4.3.14. ITCM Region Register
4.3.15. Power Control Register
4.3.16. Cache and TCM Debug Operation Register
4.3.17. RAM Access Data Registers
4.3.18. RAM Access ECC Register
4.3.19. ECC Error Registers
4.3.20. Configuration Base Address Register
4.3.21. Using the CTDOR
5. Floating Point Unit Programmers Model
5.1. About the FPU programmers model
5.1.1. FPU functionality
5.2. IEEE 754 standard compliance
5.2.1. Implementation of the IEEE 754 standard
5.2.2. IEEE 754 standard implementation choices
5.2.3. Supported formats
5.3. Instruction throughput and latency
5.3.1. Definitions of throughput and latency
5.4. Register summary
5.4.1. Processor modes for accessing the FPU system registers
5.4.2. Accessing the FPU registers
5.5. Register descriptions
5.5.1. Floating-Point System ID Register
5.5.2. Floating-Point Status and Control Register
5.5.3. Floating-Point Exception Register
6. Level One Memory System
6.1. About the L1 memory system
6.1.1. Data cache policy
6.2. Fault handling
6.2.1. Faults
6.2.2. Fault status information
6.2.3. Usage models
6.3. About the TCMs
6.4. About the caches
6.4.1. Cache maintenance operations
6.4.2. Cache error detection and correction
6.4.3. Data cache RAM organization
6.4.4. Cache interaction with memory system
6.5. Local exclusive monitor
6.6. Memory types and L1 memory system behavior
6.7. Error detection events
7. Fault Detection
7.1. About fault detection
7.1.1. RAM and logic protection
7.1.2. Analysis of errors
7.2. RAM protection
7.2.1. Protection method
7.2.2. RAM protection summary
7.2.3. ECC on RAMs
7.2.4. ECC on external AXI bus
7.2.5. ECC codes
7.2.6. RAM configuration
7.2.7. Performance impact
7.3. Logic protection
7.4. External memory and bus protection
7.4.1. Reporting errors
7.5. Programmers view
7.5.1. Registers
7.5.2. Error detection notification signals
7.6. Lock-step
7.7. Static split/lock
8. Determinism Support
8.1. About determinism support
8.2. Memory Protection Unit
8.2.1. Regions
8.2.2. Memory types
8.2.3. Region attributes
8.2.4. MPU interaction with memory system
8.2.5. MPU faults
8.2.6. MPU software-accessible registers
8.3. Branch prediction
8.4. Low latency interrupt mode
8.5. System configurability and QoS
8.6. Instruction and data TCM
9. Multiprocessing
9.1. About multiprocessing and the SCU
9.2. Multiprocessing programmers view
9.3. SCU registers
9.3.1. SCU Control Register
9.3.2. SCU Configuration Register
9.3.3. SCU CPU Power Status Register
9.3.4. SCU Invalidate All Register
9.3.5. Master Filtering Start Address Register
9.3.6. Master Filtering End Address Register
9.3.7. Peripherals Filtering Start Address Register
9.3.8. Peripherals Filtering End Address Register
9.3.9. SCU Access Control Register
9.3.10. SCU Error Bank First Entry Register
9.3.11. SCU Error Bank Second Entry Register
9.3.12. SCU Debug tag RAM access
9.4. Interrupt controller
9.4.1. About the interrupt controller
9.4.2. Distributor register descriptions
9.4.3. Interrupt interface register descriptions
9.5. Private timer and watchdog
9.5.1. Calculating timer intervals
9.5.2. Private timer and watchdog registers
9.6. Global timer
9.6.1. Global timer registers
9.7. Accelerator Coherency Port
9.7.1. Coherent and noncoherent mode
9.7.2. Read accesses in coherent mode
9.7.3. Write accesses in coherent mode
9.7.4. AXI protocol configurability, xID and AxUSER
9.7.5. AXI protocol restrictions
9.7.6. ACP bridge
10. Monitoring, Trace, and Debug
10.1. About monitoring, trace, and debug
10.2. Performance Monitoring Unit
10.2.1. PMU management registers
10.2.2. Performance monitoring events
10.3. Memory Reconstruction Port
10.4. Embedded Trace Macrocell
10.5. Debug
10.5.1. Debug events
10.5.2. Debug registers
10.5.3. External debug interface
10.5.4. Trigger inputs and outputs
11. Level Two Interface
11.1. About the L2 interface
11.1.1. Supported AXI3 transfers
11.1.2. AXI3 USER bits
11.2. Optimized accesses to the L2 memory interface
11.2.1. Early BRESP
11.2.2. SCU speculative coherent requests
11.3. Accessing RAMs using the AXI3 interface
11.4. STRT instructions
11.5. Event communication with an external agent using WFE/SEV
11.6. Accelerator Coherency Port interface
11.6.1. ACP requests
11.6.2. ACP limitations
A. Signal Descriptions
A.1. About the signal descriptions
A.2. Clock and control signals
A.3. Reset signals
A.4. Interrupt controller signals
A.5. Configuration signals
A.6. Standby signals
A.7. Power management signals
A.8. AXI3 interfaces
A.8.1. AXI master signals
A.8.2. AXI peripheral port signals
A.8.3. AXI ACP slave port signals
A.8.4. AXI TCM slave port signals
A.9. Performance monitoring signals
A.10. Exception flag signals
A.11. Error detection notification signals
A.11.1. Error detection global notification signals
A.11.2. RAM ECC error bank status signals
A.11.3. Bus ECC error signals on AXI master ports
A.11.4. Bus ECC error signals on AXI peripheral ports
A.11.5. Bus ECC error signals on AXI slave ports
A.11.6. Lock-step and split/lock signals
A.12. Test interface
A.13. MBIST interface
A.14. External debug signals
A.15. ETM/ATB interface signals
A.16. Memory reconstruction port signals
A.17. Power gating interface signals
B. Cycle Timings and Interlock Behavior
B.1. About instruction cycle timing
B.2. Data-processing instructions
B.3. Load and store instructions
B.4. Multiplication instructions
B.5. Branch instructions
B.6. Serializing instructions
B.6.1. Serializing instructions
C. Revisions

List of Figures

1. Key to timing diagram conventions
2.1. Cortex-R7 MPCore processor block diagram with two processors
2.2. Clocking example on MPCore peripherals
2.3. Powerup and powerdown sequence
4.1. MIDR bit assignments
4.2. MPUIR bit assignments
4.3. MPIDR bit assignments
4.4. REVIDR bit assignments
4.5. CCSIDR bit assignments
4.6. CLIDR bit assignments
4.7. CSSELR bit assignments
4.8. SCTLR bit assignments
4.9. ACTLR bit assignments
4.10. CPACR bit assignments
4.11. DRBAR bit assignments
4.12. DRSR bit assignments
4.13. DRACR bit assignments
4.14. RGNR bit assignments
4.15. DTCMRR bit assignments
4.16. ITCMRR bit assignments
4.17. PCR bit assignments
4.18. CTDOR bit assignments for cache RAMs
4.19. CTDOR bit assignments for TCMs
4.20. RADRLO bit assignments
4.21. RADRHI bit assignments
4.22. RAECCR bit assignments
4.23. CBAR bit assignments
5.1. FPSID Register bit assignments
5.2. FPSCR bit assignments
5.3. FPEXC Register bit assignments
6.1. Nonsequential read operation performed with one RAM access.
6.2. Sequential read operation performed with one RAM access
7.1. Lock-step
7.2. Static split/lock
8.1. Overlapping memory regions
8.2. Overlay for stack protection
8.3. Overlapping subregion of memory
9.1. SCU and ACP
9.2. SCU Control Register bit assignments
9.3. SCU Configuration Register bit assignments
9.4. SCU CPU Power Status Register bit assignments
9.5. SCU Invalidate All Register bit assignments
9.6. Master Filtering Start Address Register bit assignments
9.7. Master Filtering End Address Register bit assignments
9.8. Peripherals Filtering Start Address Register bit assignments
9.9. Peripherals Filtering End Address Register bit assignments
9.10. SCU Access Control Register bit assignments
9.11. SCU Error Bank First Entry Register bit assignments
9.12. SCU Error Bank Second Entry Register bit assignments
9.13. SCU Debug Tag RAM Operation Register bit assignments
9.14. SCU Debug Tag RAM Data Value Register bit assignments
9.15. SCU Debug Tag RAM ECC Chunk Register bit assignments
9.16. ICDDCR bit assignments
9.17. ICDICTR bit assignments
9.18. ICDIIDR bit assignments
9.19. PPI Status Register bit assignments
9.20. SPI Status Register bit assignments
9.21. SPI Status Register address map
9.22. ICCIIDR bit assignments
9.23. Private Timer Control Register bit assignments
9.24. Private Timer Interrupt Status Register bit assignments
9.25. Watchdog Control Register bit assignments
9.26. Watchdog Interrupt Status Register bit assignments
9.27. Watchdog Reset Status Register bit assignments
9.28. Global Timer Control Register bit assignments
9.29. Global Timer Interrupt Status Register bit assignments
10.1. External debug interface signals
10.2. Debug request restart-specific connections
A.1. Clocking in lock-step or split/lock implementation

List of Tables

1.
1.1. Configurable options
2.1. Reset combinations in a Cortex-R7 system
2.2. Processor power modes
2.3. AXI TCM slave port access
2.4. Doubleword accesses, aligned on 64-bit address
2.5. Single word accesses, aligned on 32-bit address
2.6. Single halfword accesses, aligned on 16-bit address
2.7. Single byte accesses
2.8. Permitted access sizes for private memory regions
2.9. Cortex-R7 MPCore private memory region
4.1. Column headings definition for CP15 register summary tables
4.2. c0 register summary
4.3. c1 register summary
4.4. c5 register summary
4.5. c6 register summary
4.6. c7 register summary
4.7. c9 register summary
4.8. c13 register summary
4.9. c15 register summary
4.10. System identification, control, and configuration registers
4.11. Fault handling registers
4.12. MPU registers
4.13. Cache maintenance registers
4.14. Interface control and configuration registers
4.15. Performance monitor registers
4.16. Miscellaneous system control registers
4.17. Implementation-defined registers
4.18. MIDR bit assignments
4.19. MPUIR bit assignments
4.20. MPIDR bit assignments
4.21. REVIDR bit assignments
4.22. CCSIDR bit assignments
4.23. CLIDR bit assignments
4.24. CSSELR bit assignments
4.25. SCTLR bit assignments
4.26. ACTLR bit assignments
4.27. CPACR bit assignments
4.28. DRBAR bit assignments
4.29. DRSR bit assignments
4.30. DRACR bit assignments
4.31. Access data permission bit encoding
4.32. RGNR bit assignments
4.33. DTCMRR bit assignments
4.34. ITCMRR bit assignments
4.35. PCR bit assignments
4.36. CTDOR bit assignments for cache RAMs
4.37. CTDOR bit assignments for TCMs
4.38. RAECCR bit assignments
4.39. DEER0-2 bit assignments
4.40. IEER0-2 bit assignments
4.41. DTCMEER/ITCMEER bit assignments
4.42. Error status bit encoding
5.1. FPU instruction throughput and latency cycles
5.2. FPU system registers
5.3. Accessing FPU system registers
5.4. FPSID Register bit assignments
5.5. FPSCR bit assignments
5.6. FPEXC Register bit assignments 
6.1. Types of aborts
6.2. Cache ECC error behavior
6.3. Tag RAM bit descriptions, with ECC
6.4. Tag RAM bit descriptions, no ECC
6.5. Cache sizes and tag RAM organization
6.6. Instruction cache data RAM sizes, no ECC
6.7. Data cache data RAM sizes, no ECC
6.8. Instruction cache data RAM sizes with ECC
6.9. Data cache data RAM sizes with ECC
6.10. Data cache RAM bits, with ECC
6.11. Memory types and associated behavior
7.1. RAM protection summary
7.2. Basic ECC scheme per RAM type
7.3. RAM configuration with or without ECC
7.4. RAM configuration with or without parity
8.1. Memory attributes summary
8.2. TEX[2:0], C, and B encodings
8.3. Inner and Outer cache policy encoding
8.4. Performance and determinism effects in low latency interrupt mode
8.5. Recommended QoS bit settings according to traffic types
9.1. Peripheral accesses
9.2. SCU registers summary
9.3. SCU Control Register bit assignments
9.4. SCU Configuration Register bit assignments
9.5. SCU CPU Power Status Register bit assignments
9.6. SCU Invalidate All Register bit assignments
9.7. Master Filtering Start Address Register bit assignments
9.8. Master Filtering End Address Register bit assignments
9.9. Peripherals Filtering Start Address Register bit assignments
9.10. Peripherals Filtering End Address Register bit assignments
9.11. SCU Access Control Register bit assignments
9.12. SCU Error Bank First Entry Register bit assignments
9.13. SCU Error Bank Second Entry Register bit assignments
9.14. SCU Debug Tag RAM Operation Register bit assignments
9.15. SCU Debug Tag RAM Data Value Register bit assignments
9.16. SCU Debug Tag RAM ECC Chunk Register bit assignments
9.17. Distributor register summary
9.18. ICDDCR bit assignments
9.19. ICDICTR bit assignments
9.20. ICDIIDR bit assignments
9.21. PPI Status Register bit assignments
9.22. SPI Status Register bit assignments
9.23. Cortex-R7 processor interface register summary
9.24. ICCIIDR bit assignments
9.25. Timer and watchdog registers 
9.26. Private Timer Control Register bit assignments 
9.27. Watchdog Control Register bit assignments 
9.28. Global timer registers
9.29. Global Timer Control Register bit assignments 
9.30. AWUSERSC encoding for ACP
9.31. ARUSERSC encoding for ACP
10.1. Performance monitoring instructions and Debug APB mapping
10.2. PMU management registers
10.3. Processor Identifier Registers
10.4. Peripheral Identification Registers
10.5. Component Identification Registers
10.6. PMU register names and APB addresses
10.7. Cortex-R7 MPCore processor events
10.8. Debug register mapping
10.9. Debug management registers
10.10. Processor ID Registers
10.11. Peripheral Identification Registers for processor debug
10.12. Component Identification Registers
10.13. Authentication signal restrictions
10.14. PADDRDBG[16:2] mapping
10.15. Trigger inputs
10.16. Trigger outputs
11.1. AXI3 master 0 and master 1 interface attributes
11.2. ARUSERM0[8:0] encodings
11.3. ARUSERM1[8:0] encodings
11.4. ARUSERMP[8:0] encodings
11.5. AWUSERM0[10:0] encodings
11.6. AWUSERM1[10:0] encodings
11.7. AWUSERMP[10:0] encodings
11.8. WUSERM0[1:0] encodings
11.9. WUSERM1[1:0] encodings
11.10. WUSERMP[1:0] encodings
11.11. TCM accesses
11.12. MSB bit for the different TCM RAM sizes
11.13. Cortex-R7 processor mode and AxPROT values
A.1. Clock and clock control signals
A.2. Reset signals
A.3. Interrupt controller signals
A.4. Configuration signals
A.5. Standby and Wait for event signals
A.6. Event signals
A.7. Power management signals
A.8. AXI master interface clock enable signals
A.9. AXI master read address signals
A.10. AXI master read data signals
A.11. AXI master write address signals
A.12. AXI master write data signals
A.13. AXI master write response signals
A.14. Clock enable signals
A.15. AXI peripheral port read address signals
A.16. AXI peripheral port read data signals
A.17. AXI peripheral port write address signals
A.18. AXI peripheral port write data signals
A.19. AXI peripheral port write response signals
A.20. AXI ACP slave port clock enable signal
A.21. AXI ACP slave port read address signals
A.22. AXI ACP slave port read data signals
A.23. AXI ACP slave port write address signals
A.24. AXI ACP slave port write data signals
A.25. AXI ACP slave port write response signals
A.26. AXI TCM slave port clock enable signal
A.27. AXI TCM slave port read address signals
A.28. AXI TCM slave port read data signals
A.29. AXI TCM slave port write address signals
A.30. AXI TCM slave port write data signals
A.31. AXI TCM slave port write response signals
A.32. Performance monitoring signals
A.33. Exception flag signals
A.34. Error detection global notification signals
A.35. RAM ECC error bank status signals
A.36. Bus ECC error signals on AXI master ports
A.37. Bus ECC error signals on AXI peripheral ports
A.38. Bus ECC error signals on AXI slave ports
A.39. Lock-step and split/lock signals
A.40. Test interface signals
A.41. L1 and DTCM Cortex-R7 MBIST interface width without ECC
A.42. L1 and DTCM Cortex-R7 MBIST interface width with ECC
A.43. ITCM Cortex-R7 MBIST interface width without ECC
A.44. ITCM Cortex-R7 MBIST interface width with ECC
A.45. Debug enable signals
A.46. Debug signals
A.47. Miscellaneous debug signals
A.48. Debug APB interface signals
A.49. ETM/ATB interface signals for data trace
A.50. ETM/ATB interface signals for instruction trace
A.51. Miscellaneous trace signals
A.52. CTI signals
A.53. Memory reconstruction port signals
A.54. Power gating interface signals
B.1. Data-processing instructions cycle timings
B.2. Single load and store operation cycle timings
B.3. Load multiple operations cycle timings
B.4. Store multiple operations cycle timings
B.5. Multiplication instruction cycle timings
C.1. Issue A
C.2. Differences between issue A and issue B
C.3. Differences between issue B and issue C

Proprietary Notice

This document is protected by copyright and other related rights and the practice or implementation of the information contained in this document may be protected by one or more patents or pending patent applications. No part of this document may be reproduced in any form by any means without the express prior written permission of ARM. No license, express or implied, by estoppel or otherwise to any intellectual property rights is granted by this document unless specifically stated.

Your access to the information in this document is conditional upon your acceptance that you will not use or permit others to use the information for the purposes of determining whether implementations infringe any third party patents.

THIS DOCUMENT IS PROVIDED “AS IS”. ARM PROVIDES NO REPRESENTATIONS AND NO WARRANTIES, EXPRESS, IMPLIED OR STATUTORY, INCLUDING, WITHOUT LIMITATION, THE IMPLIED WARRANTIES OF MERCHANTABILITY, SATISFACTORY QUALITY, NON-INFRINGEMENT OR FITNESS FOR A PARTICULAR PURPOSE WITH RESPECT TO THE DOCUMENT. For the avoidance of doubt, ARM makes no representation with respect to, and has undertaken no analysis to identify or understand the scope and content of, third party patents, copyrights, trade secrets, or other rights.

This document may include technical inaccuracies or typographical errors.

TO THE EXTENT NOT PROHIBITED BY LAW, IN NO EVENT WILL ARM BE LIABLE FOR ANY DAMAGES, INCLUDING WITHOUT LIMITATION ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL, PUNITIVE, OR CONSEQUENTIAL DAMAGES, HOWEVER CAUSED AND REGARDLESS OF THE THEORY OF LIABILITY, ARISING OUT OF ANY USE OF THIS DOCUMENT, EVEN IF ARM HAS BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.

This document consists solely of commercial items. You shall be responsible for ensuring that any use, duplication or disclosure of this document complies fully with any relevant export laws and regulations to assure that this document or any portion thereof is not exported, directly or indirectly, in violation of such export laws. Use of the word “partner” in reference to ARM’s customers is not intended to create or refer to any partnership relationship with any other company. ARM may make changes to this document at any time and without notice.

If any of the provisions contained in these terms conflict with any of the provisions of any signed written agreement covering this document with ARM, then the signed written agreement prevails over and supersedes the conflicting provisions of these terms. This document may be translated into other languages for convenience, and you agree that if there is any conflict between the English version of this document and any translation, the terms of the English version of the Agreement shall prevail.

Words and logos marked with ® or ™ are registered trademarks or trademarks of ARM Limited or its affiliates in the EU and/or elsewhere. All rights reserved. Other brands and names mentioned in this document may be the trademarks of their respective owners. Please follow ARM’s trademark usage guidelines at http://www.arm.com/about/trademark-usage-guidelines.php

http://www.arm.com/about/trademark-usage-guidelines.php

Copyright ©, ARM Limited or its affiliates. All rights reserved.

ARM Limited. Company 02557590 registered in England.

110 Fulbourn Road, Cambridge, England CB1 9NJ.

Confidentiality Status

This document is Non-Confidential. The right to use, copy and disclose this document may be subject to license restrictions in accordance with the terms of the agreement entered into by ARM and the party that ARM delivered this document to.

Product Status

The information in this document is final, that is for a developed product.

Revision History
Revision A21 March 2012First release for r0p0
Revision B28 September 2012First release for r0p1
Revision C28 November 2014Second release for r0p1
Copyright © 2012, 2014 ARM. All rights reserved.ARM DDI 0458C
Non-ConfidentialID112814