Using this book

This book is organized into the following chapters:

Chapter 1 Introduction

Read this for an introduction to the Cortex-R7 MPCore processor.

Chapter 2 Functional Description

Read this for descriptions of the major functional blocks.

Chapter 3 Programmers Model

Read this for a description of the Cortex-R7 MPCore processor registers and programming information.

Chapter 4 System Control

Read this for a description of the system control coprocessor registers and programming information.

Chapter 5 Floating Point Unit Programmers Model

Read this for a description of the Floating Point Unit (FPU) support.

Chapter 6 Level One Memory System

Read this for a description of the Level One (L1) memory system.

Chapter 7 Fault Detection

Read this for a description of the fault detection features, including Error Correcting Code (ECC), lock-step, and split/lock.

Chapter 8 Determinism Support

Read this for a description of the determinism support features, including the Memory Protection Unit (MPU) and Quality of Service (QoS).

Chapter 9 Multiprocessing

Read this for a description of the multiprocessing features, including the Snoop Control Unit (SCU), interrupt controller, timers and watchdog, and Accelerator Coherency Port (ACP).

Chapter 10 Monitoring, Trace, and Debug

Read this for a description of the monitoring, trace, and debug features, and the Integration Test Registers.

Chapter 11 Level Two Interface

Read this for a description of the Level Two (L2) interface.

Appendix A Signal Descriptions

Read this for a description of the Cortex-R7 MPCore processor signals.

Appendix B Cycle Timings and Interlock Behavior

Read this for a description of the Cortex-R7 MPCore instruction cycle timing.

Appendix C Revisions

Read this for a description of the technical changes between released issues of this book.

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