CoreSight™ ETM™-R7 Technical Reference Manual

Revision: r0p1

Table of Contents

About this book
Product revision status
Intended audience
Using this book
Additional reading
Feedback on this product
Feedback on content
1. Introduction
1.1. About the ETM-R7
1.1.1. The CoreSight debug environment
1.2. Compliance
1.2.1. Trace macrocell
1.2.2. Advanced Microcontroller Bus Architecture
1.3. Features
1.4. Interfaces
1.5. Configurable options
1.6. Test features
1.7. Product documentation and design flow
1.7.1. Documentation
1.7.2. Design flow
1.8. Product revisions
2. Functional Description
2.1. About the functions
2.1.1. Processor interface
2.1.2. Instruction trace generator
2.1.3. Data trace generator
2.1.4. FIFO
2.1.5. Resources and filtering logic
2.1.6. ATB interface
2.1.7. APB interface
2.1.8. Global timestamping
2.2. Interfaces
2.2.1. CPU PMU connectivity
2.3. Clocking and resets
2.3.1. ETM-R7 clock
2.3.2. ETM-R7 low power control
2.3.3. ETM-R7 reset
2.3.4. Access permissions and power domains
2.4. Operation
2.4.1. Implementation-defined registers
2.4.2. Precise TraceEnable events
2.4.3. Parallel instruction execution
2.4.4. Context ID tracing
2.4.5. Trace and comparator features
2.4.6. Data address range filtering
2.4.7. Interaction with the PMU
2.4.8. Packet formats
2.4.9. Resource selection
2.4.10. Trace flush behavior
2.4.11. Low power state behavior
2.4.12. Cycle counter
2.4.13. Micro-architectural exceptions
2.4.14. Synchronization
3. Programmers Model
3.1. About the programmers model
3.2. Modes of operation and execution
3.2.1. Controlling ETM programming
3.2.2. Programming and reading ETM registers
3.3. Register summary
3.3.1. Functional grouping of registers
3.4. Register descriptions
3.4.1. Programming Control Register
3.4.2. Processor Select Control Register
3.4.3. Status Register
3.4.4. Trace Configuration Register
3.4.5. Auxiliary Control Register
3.4.6. Event Control 0 Register
3.4.7. Event Control 1 Register
3.4.8. Stall Control Register
3.4.9. Global Timestamp Control Register
3.4.10. Synchronization Period Register
3.4.11. Cycle Count Control Register
3.4.12. Branch Broadcast Control Register
3.4.13. Trace ID Register
3.4.14. ViewInst Main Control Register
3.4.15. ViewInst Include/Exclude Control Register
3.4.16. ViewInst Start/Stop Control Register
3.4.17. ViewData Main Control Register
3.4.18. ViewData Include/Exclude Single Address Comparator Register
3.4.19. ViewData Include/Exclude Address Range Comparator Register
3.4.20. Sequencer State Transition Control Registers 0-2
3.4.21. Sequencer Reset Control Register
3.4.22. Sequencer State Register
3.4.23. External Input Select Register
3.4.24. Counter Reload Value Registers 0-1
3.4.25. Counter Control Register 0
3.4.26. Counter Control Register 1
3.4.27. Counter Value Registers 0-1
3.4.28. ID Register 8-13
3.4.29. Implementation Specific Register 0
3.4.30. ID Register 0
3.4.31. ID Register 1
3.4.32. ID Register 2
3.4.33. ID Register 3
3.4.34. ID Register 4
3.4.35. ID Register 5
3.4.36. Resource Selection Registers 2-16
3.4.37. Single-Shot Comparator Control Registers 0-1
3.4.38. Single-Shot Comparator Status Registers 0-1
3.4.39. OS Lock Access Register
3.4.40. OS Lock Status Register
3.4.41. Power Down Control Register
3.4.42. Power Down Status Register
3.4.43. Address Comparator Value Registers 0-7
3.4.44. Address Comparator Access Type Registers 0-7
3.4.45. Data Value Comparator Value Registers 0-1
3.4.46. Data Value Comparator Mask Registers 0-1
3.4.47. Context ID Comparator Value Register 0
3.4.48. Context ID Comparator Control Register 0
3.4.49. Integration Mode Control Register
3.4.50. Claim Tag Set Register
3.4.51. Claim Tag Clear Register
3.4.52. Device Affinity Register
3.4.53. Software Lock Access Register
3.4.54. Software Lock Status Register
3.4.55. Authentication Status Register
3.4.56. Device Architecture Register
3.4.57. Device ID Register
3.4.58. Device Type Register
3.4.59. Peripheral Identification Registers
3.4.60. Component Identification Registers
3.4.61. Integration Test Registers
A. Signal Descriptions
A.1. Signal descriptions
A.2. Clocks and resets
A.3. Processor trace interface
A.4. APB interface
A.5. ATB interface
A.6. Miscellaneous signals
A.7. Test interface
B. Revisions

List of Figures

1. Key to timing diagram conventions
1.1. ETM-R7 system diagram
2.1. ETM-R7 block diagram
2.2. Trigger event resource selection
3.1. Programming ETM-R7 registers
3.2. TRCPRGCTLR bit assignments
3.3. TRCPROCSELR bit assignments
3.4. TRCSTATR bit assignments
3.5. TRCCONFIGR bit assignments
3.6. TRCAUXCTLR bit assignments
3.7. TRCEVENTCTL0R bit assignments
3.8. TRCEVENTCTL1R bit assignments
3.9. TRCSTALLCTLR bit assignments
3.10. TRCTSCTLR bit assignments
3.11. TRCSYNCPR bit assignments
3.12. TRCCCCTLR bit assignments
3.13. TRCBBCTLR bit assignments
3.14. TRCTRACEIDR bit assignments
3.15. TRCVICTLR bit assignments
3.16. TRCVIIECTLR bit assignments
3.17. TRCVISSCTLR bit assignments
3.18. TRCVDCTLR bit assignments
3.19. TRCVDSACCTLR bit assignments
3.20. TRCVDARCCTLR bit assignments
3.21. TRCSEQEVRn bit assignments
3.22. TRCSEQRSTEVR bit assignments
3.23. TRCSEQSTR bit assignments
3.24. TRCEXTINSELR bit assignments
3.25. TRCCNTRLDVRn bit assignments
3.26. TRCCNTCTLR0 bit assignments
3.27. TRCCNTCTLR1 bit assignments
3.28. TRCCNTVRn bit assignments
3.29. TRCIDR8 bit assignments
3.30. TRCIDR9 bit assignments
3.31. TRCIDR10 bit assignments
3.32. TRCIDR11 bit assignments
3.33. TRCIDR12 bit assignments
3.34. TRCIDR13 bit assignments
3.35. TRCIMSPEC0 bit assignments
3.36. TRCIDR0 bit assignments
3.37. TRCIDR1 bit assignments
3.38. TRCIDR2 bit assignments
3.39. TRCIDR3 bit assignments
3.40. TRCIDR4 bit assignments
3.41. TRCIDR5 bit assignments
3.42. TRCRSCTLRn bit assignments
3.43. TRCSSCCRn bit assignments
3.44. TRCSSCSRn bit assignments
3.45. TRCOSLAR bit assignments
3.46. TRCOSLSR bit assignments
3.47. TRCPDCR bit assignments
3.48. TRCPDSR bit assignments
3.49. TRCACVRn bit assignments
3.50. TRCACATR0 bit assignments
3.51. TRCACATR1 bit assignments
3.52. TRCDVCVRn bit assignments
3.53. TRCDVCMRn bit assignments
3.54. TRCCIDCVR0 bit assignments
3.55. TRCCIDCCTLR0 bit assignments
3.56. TRCITCTRL bit assignments
3.57. TRCCLAIMSET bit assignments
3.58. TRCCLAIMCLR bit assignments
3.59. TRCDEVAFF0 bit assignments
3.60. TRCLAR bit assignments
3.61. TRCLSR bit assignments
3.62. TRCAUTHSTATUS bit assignments
3.63. TRCDEVARCH bit assignments
3.64. TRCDEVID bit assignments
3.65. TRCDEVTYPE bit assignments
3.66. Mapping between TRCPIDR0-7 and the Peripheral ID value
3.67. Peripheral ID fields
3.68. Mapping between TRCCIDR0-3 and the Component ID value
3.69. TRCITMISCOUTR bit assignments
3.70. TRCITMISCINR bit assignments
3.71. TRCITATBIDR bit assignments
3.72. TRCITDDATAR bit assignments
3.73. TRCITIDATAR bit assignments
3.74. TRCITDATBINR bit assignments
3.75. TRCITIATBINR bit assignments
3.76. TRCITDATBOUTR bit assignments
3.77. TRCITIATBOUTR bit assignments

List of Tables

1.1. ETM-R7 features with implementation-defined number of instances or size
1.2. ETM-R7 implementation of optional features
2.1. ETMEVENT connections
2.2. ETM EXTOUT connections to CTI and processor PMU
2.3. Resource selection
3.1. ETM-R7 register summary
3.2. General control and ID registers
3.3. Trace filtering control registers
3.4. Derived resource registers
3.5. Implementation-specific and identification registers
3.6. Resource selection registers
3.7. Single-Shot Comparator registers
3.8. OS lock and power control registers
3.9. Comparator registers
3.10. Integration Test registers
3.11. CoreSight management registers
3.12. TRCPRGCTLR bit assignments
3.13. TRCPROCSELR bit assignments
3.14. TRCSTATR bit assignments
3.15. TRCCONFIGR bit assignments
3.16. TRCAUXCTLR bit assignments
3.17. TRCEVENTCTL0R bit assignments
3.18. TRCEVENTCTL1R bit assignments
3.19. TRCSTALLCTLR bit assignments
3.20. TRCTSCTLR bit assignments
3.21. TRCSYNCPR bit assignments
3.22. TRCCCCTLR bit assignments
3.23. TRCBBCTLR bit assignments
3.24. TRCTRACEIDR bit assignments
3.25. TRCVICTLR bit assignments
3.26. TRCVIIECTLR bit assignments
3.27. TRCVISSCTLR bit assignments
3.28. TRCVDCTLR bit assignments
3.29. TRCVDSACCTLR bit assignments
3.30. TRCVDARCCTLR bit assignments
3.31. TRCSEQEVRn bit assignments
3.32. TRCSEQRSTEVR bit assignments
3.33. TRCSEQSTR bit assignments
3.34. TRCEXTINSELR bit assignments
3.35. TRCCNTRLDVRn bit assignments
3.36. TRCCNTCTLR0 bit assignments
3.37. TRCCNTCTLR1 bit assignments
3.38. TRCCNTVRn bit assignments
3.39. TRCIDR8 bit assignments
3.40. TRCIDR9 bit assignments
3.41. TRCIDR10 bit assignments
3.42. TRCIDR11 bit assignments
3.43. TRCIDR12 bit assignments
3.44. TRCIDR13 bit assignments
3.45. TRCIMSPEC0 bit assignments
3.46. TRCIDR0 bit assignments
3.47. TRCIDR1 bit assignments
3.48. TRCIDR2 bit assignments
3.49. TRCIDR3 bit assignments
3.50. TRCIDR4 bit assignments
3.51. TRCIDR5 bit assignments
3.52. TRCRSCTLRn bit assignments
3.53. TRCSSCCRn bit assignments
3.54. TRCSSCSR0 bit assignments
3.55. TRCSSCSR1 bit assignments
3.56. TRCOSLAR bit assignments
3.57. TRCOSLSR bit assignments
3.58. TRCPDCR bit assignments
3.59. TRCPDSR bit assignments
3.60. TRCACVRn bit assignments
3.61. TRCACATR0 bit assignments
3.62. TRCACATR1 bit assignments
3.63. TRCDVCVRn bit assignments
3.64. TRCDVCMRn bit assignments
3.65. TRCCIDCVR0 bit assignments
3.66. TRCCIDCCTLR0 bit assignments
3.67. TRCPRGCTLR bit assignments
3.68. TRCCLAIMSET bit assignments
3.69. TRCCLAIMCLR bit assignments
3.70. TRCDEVAFF0 bit assignments
3.71. TRCLAR bit assignments
3.72. TRCLSR bit assignments
3.73. TRCAUTHSTATUS bit assignments
3.74. TRCDEVARCH bit assignments
3.75. TRCDEVID bit assignments
3.76. TRCDEVTYPE bit assignments
3.77. TCRPIDR0-7 bit assignments
3.78. TRCCIDR0-3 bit assignments
3.79. Output signals that the Integration Test Registers can control
3.80. Input signals that the Integration Test Registers can read
3.81. TRCITMISCOUTR bit assignments
3.82. TRCITMISCINR bit assignments
3.83. TRCITATBIDR bit assignments
3.84. TRCITDDATAR bit assignments
3.85. TRCITIDATAR bit assignments
3.86. TRCITDATBINR bit assignments
3.87. TRCITIATBINR bit assignments
3.88. TRCITDATBOUTR bit assignments
3.89. TRCITIATBOUTR bit assignments
A.1. ETM-R7 signals
A.2. Clock and reset signals
A.3. Processor trace interface signals
A.4. APB signals
A.5. ATB signals for instruction trace
A.6. ATB signals for data trace
A.7. Miscellaneous signals
A.8. Test signal
B.1. Issue A
B.2. Differences between issue A and issue B

Proprietary Notice

Words and logos marked with ® or ™ are registered trademarks or trademarks of ARM in the EU and other countries, except as otherwise stated below in this proprietary notice. Other brands and names mentioned herein may be the trademarks of their respective owners.

Neither the whole nor any part of the information contained in, or the product described in, this document may be adapted or reproduced in any material form except with the prior written permission of the copyright holder.

The product described in this document is subject to continuous developments and improvements. All particulars of the product and its use contained in this document are given by ARM in good faith. However, all warranties implied or expressed, including but not limited to implied warranties of merchantability, or fitness for purpose, are excluded.

This document is intended only to assist the reader in the use of the product. ARM shall not be liable for any loss or damage arising from the use of any information in this document, or any error or omission in such information, or any incorrect use of the product.

Where the term ARM is used it means “ARM or any of its subsidiaries as appropriate”.

Confidentiality Status

This document is Non-Confidential. The right to use, copy and disclose this document may be subject to license restrictions in accordance with the terms of the agreement entered into by ARM and the party that ARM delivered this document to.

Product Status

The information in this document is final, that is for a developed product.

Revision History
Revision A21 March 2012First release for r0p0
Revision B28 September 2012First release for r0p1
Copyright © 2012 ARM. All rights reserved.ARM DDI 0459B