Glossary

This glossary describes some of the terms used in technical documents from ARM.

Abort

An exception caused by an illegal memory access. Aborts can be caused by the external memory system or by the memory-management hardware, that might include a Memory Management Unit (MMU) or a Memory Protection Unit (MPU).

See Also Data abort, External abort and Prefetch abort.

Abort model

Describes what happens to the processor state when a Data abort exception occurs. Different abort models behave differently with regard to load and store instructions that specify base register write-back.

Addressing mode

A method for generating the memory address used by a load or store instruction.

Advanced eXtensible Interface (AXI)

A bus protocol that supports separate phases for address or control and data, unaligned data transfers using byte strobes, burst-based transactions with only start address issued, separate read and write data channels, issuing multiple outstanding addresses, out-of-order transaction completion, and easy addition of register stages to provide timing closure.

The AXI protocol includes optional extensions for signaling for low-power operation.

Advanced High-performance Bus (AHB)

A bus protocol with a fixed pipeline between the address or control and data phases. It supports a subset of the functionality of the AMBA AXI protocol. The full AMBA AHB protocol specification includes a number of features that are not commonly required for master and slave implementations and ARM recommends using the AMBA AHB-Lite subset of the protocol.

See Also Advanced Microcontroller Bus Architecture (AMBA) and AHB-Lite.

Advanced Microcontroller Bus Architecture (AMBA)

The AMBA family of protocol specifications is the ARM open standard for on-chip buses. AMBA provides a strategy for the interconnection and management of the functional blocks that make up a System-on-Chip (SoC). Applications include the development of embedded systems with one or more processors or signal processors and multiple peripherals. AMBA defines a common backbone for SoC modules, and therefore complements a reusable design methodology.

Advanced Peripheral Bus (APB)

A bus protocol that is designed for use with ancillary or general-purpose peripherals such as timers, interrupt controllers, UARTs, and I/O ports. It connects to the main system bus through a system-to-peripheral bus bridge that helps reduce system power consumption.

Advanced SIMD

An extension to the ARM architecture that provides Single Instruction Multiple Data (SIMD) operations on a bank of extension registers. If a floating-point extension is also implemented, the two extensions share a common extension register bank. The Advanced SIMD extension implements NEON technology, and is often called NEON.

AHB

See Advanced High-performance Bus (AHB).

AHB-Lite

A subset of the full AMBA AHB protocol specification. It provides all of the basic functions required by the majority of AMBA AHB slave and master designs, particularly when used with a multi-layer AMBA interconnect. In most cases, the extra facilities provided by a full AMBA AHB interface are implemented more efficiently using an AMBA AXI protocol interface.

Aligned

A data item stored at an address that is divisible by the number of bytes that defines its data size is said to be aligned. Aligned doublewords, words, and halfwords have addresses that are divisible by eight, four, and two respectively. The terms doubleword-aligned, word-aligned, and halfword-aligned therefore stipulate addresses that are divisible by eight, four, and two respectively. An aligned access is one where the address of the access is aligned to the size of an element of the access.

AMBA

See Advanced Microcontroller Bus Architecture (AMBA).

APB

See Advanced Peripheral Bus (APB).

ARM instruction

A word that specifies an operation for a processor in ARM state to perform. ARM instructions must be word-aligned.

ARM state

In ARM state the processor executes the ARM instruction set.

AXI

See Advanced eXtensible Interface (AXI).

AXI channels, channel order and interfaces

The block diagram shows:

  • the order in which AXI channel signals are described

  • the master and slave interface conventions for AXI components.

AXI signal names have a one or two letter prefix that denotes the AXI channel as follows:

AW

Write address channel.

W

Write data channel.

B

Write response channel.

AR

Read address channel.

R

Read data channel.

General descriptions of AXI signals use x to represent this prefix, for example, xVALID and xREADY.

AXI terminology

The following general AXI terms apply to both masters and slaves:

Active read transaction

A transaction for which the read address transfer has been completed, but the last read data transfer has not been completed.

Active transfer

A transfer for which the transmitting interface has asserted the xVALID handshake signal, but the receiving interface has not asserted the xREADY handshake signal.

Active write transaction

A transaction for which the write address or leading write data transfer has been completed, but the write response has not been completed.

Completed transfer

A transfer for which the handshake using xVALID and xREADY is complete.

Payload

The non-handshake signals in a transfer.

Transaction

An entire burst of transfers, comprising an address transfer, one or more data transfers and, for write transactions only, a response transfer.

Transmitting interface

An initiator driving the payload and asserting the relevant xVALID signal.

Transfer

A single exchange of information. That is, a transfer with a single handshake using xVALID and xREADY.

The following AXI terms are master interface attributes. To permit system performance optimization, they must be specified for every component with an AXI master interface:

Combined issuing capability

The maximum number of active transactions that the interface can generate. It is specified for master interfaces that use combined storage for active write and read transactions. If not specified you can assume it is equal to the sum of the write and read issuing capabilities.

Read ID capability

The maximum number of different ARID values that the interface can generate for all active read transactions at any one time.

Read ID width

The number of bits in the ARID bus.

Read issuing capability

The maximum number of active read transactions that the interface can generate. Must be specified if the combined issuing capability is not specified.

Write ID capability

The maximum number of different AWID values that the interface can generate for all active write transactions at any one time.

Write ID width

The number of bits in the AWID and WID buses.

Write interleave capability

The number of active write transactions for which the interface can transmit data. This is counted from the earliest transaction.

Write issuing capability

The maximum number of active write transactions that a master interface can generate. Must be specified if the combined issuing capability is not specified.

The following AXI terms are slave interface attributes. To permit performance optimization, they must be specified for every component with an AXI slave interface:

Combined acceptance capability

The maximum number of active transactions that the interface can accept. It is specified for slave interfaces that use combined storage for active write and read transactions. If not specified then you can assume it is equal to the sum of the write and read acceptance capabilities.

Read acceptance capability

The maximum number of active read transactions that the interface can accept. Must be specified if the combined acceptance capability is not specified.

Read data reordering depth

The number of active read transactions for which the interface can transmit data. This is counted from the earliest transaction.

Write acceptance capability

The maximum number of active write transactions that the interface can accept. Must be specified if the combined acceptance capability is not specified.

Write interleave depth

The number of active write transactions for which the interface can receive data. This is counted from the earliest transaction.

Banked registers

A register that has multiple instances, with the instance that is in use dependent on a property of the state of the device, for example the processor mode or security state.

Base register

A register specified by a load or store instruction that is used as the base value for the address calculation for the instruction. Depending on the instruction and its addressing mode, an offset can be added to or subtracted from the base register value to form the virtual address that is sent to memory.

Base register write-back

Writing back a modified value to the base register used in an address calculation.

Beat

Alternative word for an individual transfer within a burst. For example, an INCR4 burst comprises four beats.

See Also Burst.

Boundary scan chain

A boundary scan chain is made up of serially-connected devices that implement boundary scan technology using a standard JTAG TAP interface. Each device contains at least one TAP controller containing shift registers that form the chain, connected between TDI and TDO, through which test data is shifted. A processor can contain several shift registers, enabling you to access selected parts of the device.

Branch prediction

A technique where a processor chooses a future execution path to prefetch along. For example, after a branch instruction, the processor can choose to prefetch either the instruction following the branch or the instruction at the branch target.

See Also Prefetching.

Breakpoint

A breakpoint is a debug event triggered by the execution of a particular instruction. It is specified in terms of one or both of the address of the instruction and the state of the processor when the instruction is executed.

See Also Watchpoint.

Burst

A group of transfers to consecutive addresses. Because the addresses are consecutive, the device transmitting the data does not have to supply an address for any transfer after the first one. This increases the speed at which the burst occurs. If using an AMBA interface, the transmitting device controls the burst using signals that indicate the length of the burst and how the addresses are incremented.

See Also Beat.

Byte lane strobe

A signal that determines which byte lanes are active, or valid, in a data transfer. Each bit of this signal corresponds to eight bits of the data bus.

Byte-invariant

In a byte-invariant system, the address of each byte of memory remains unchanged when switching between little-endian and big-endian operation. When a data item larger than a byte is loaded from or stored to memory, the bytes making up that data item are arranged into the correct order depending on the endianness of the memory access.

The ARM architecture supports byte-invariant systems in ARMv6 and later versions.

When byte-invariant support is selected, unaligned halfword and word memory accesses are also supported. The architecture requires multi-word accesses to be word-aligned.

See Also Word-invariant.

Cache hit

A memory access that can be processed at high speed because the instruction or data that it addresses is already held in the cache.

Cache line

The basic unit of storage in a cache. Its size in words is always a power of two, usually four or eight words. A cache line must be aligned to a suitable memory boundary.

See Also Cache terminology diagram.

Cache miss

A memory access that cannot be processed at high speed because the instruction or data it addresses is not in the cache.

Cache sets

Areas of a cache, divided up to simplify and speed up the process of determining whether a cache hit occurs. In the ARM architecture, the number of cache sets is always a power of two.

See Also Cache terminology diagram.

Cache terminology

See the Cache terminology diagram and the entries for terms used in that diagram.

Cache terminology diagram

The diagram illustrates the following cache terminology:

  • block address

  • cache line

  • cache set

  • cache way

  • index

  • tag.

Cache way

A cache way consists of one cache line from each cache set. The cache ways are indexed from 0 to ASSOCIATIVITY-1. Each cache lines in a cache way has the same index as the cache way. For example cache way n consists of the cache line with index n from each cache set.

See Also Cache terminology diagram.

CDP instruction

Coprocessor data processing instruction. For the VFP coprocessor, CDP instructions are arithmetic instructions and FCPY, FABS, and FNEG.

Clean

A cache line that has not been modified while it is in the cache is said to be clean. To clean a cache is to write dirty cache entries into main memory. If a cache line is clean, it is not written on a cache miss because the next level of memory contains the same data as the cache.

See Also Dirty.

Clock gating

Gating a clock signal for a macrocell or functional block with a control signal and using the modified clock that results to control the operating state of the macrocell or block.

Clocks Per Instruction (CPI)

See Cycles Per Instruction (CPI).

Coherency

See Memory coherency.

Cold reset

Also known as power-on reset. Starting the processor by turning power on. Turning power off and then back on again clears main memory and many internal settings. Some program failures can lock up the processor and require a cold reset to restart the system. In other cases, only a warm reset is required.

See Also Warm reset.

Communications channel

The hardware used for communicating between the software running on the processor, and an external host, using the debug interface. When this communication is for debug purposes, it is called the Debug Communications Channel (DCC). From ARMv6, the DCC includes the Data Transfer Register, some bits in the Data Status and Control Register, and the external debug interface controller, such as the DBGTAP controller in the case of a JTAG interface.

Condition field

A four-bit field in an ARM instruction that specifies a condition under which the instruction executes.

See Also Conditional execution.

Conditional execution

For ARM instructions, if the condition field indicates that the corresponding condition is true when the instruction starts executing, it executes normally. Otherwise, the instruction does nothing.

In the Thumb instruction set, the IT instruction makes up to four of the following instructions conditional.

Context switch

The saving and restoring of computational state when switching between different threads or processes. In ARM documentation, the term context switch describes any situation where the context is switched by an operating system and might or might not include changes to the address space.

Coprocessor

A processor that supplements the main processor to carry out additional functions that the main processor cannot perform. The ARM architecture defines an interface to up to 16 coprocessors, CP0-CP15 for use by ARM:

  • CP15 instructions access the System Control processor

  • CP14 instructions access control registers for debug, trace, and execution environment features

  • CP10 an CP11 instruction space is for floating-point and Advanced SIMD instructions if supported.

Core register

One of the 32-bit general-purpose integer registers, R0 to R15. R15 is an alias for PC, the Program Counter.

R14 is an alias for LR, the Link Register, and R13 is an alias for SP, the Stack Pointer.

See the appropriate ARM Architectural Reference Manual for the constraints on the use of PC, LR, and SP.

CoreSight

ARM on-chip debug and trace components, that provide the infrastructure for monitoring, tracing, and debugging a complete system on chip.

CPI

See Cycles Per Instruction (CPI).

CPSR

See Current Program Status Register (CPSR).

Cross Trigger Interface (CTI)

Part of an Embedded Cross Trigger (ECT) device. In an ECT, the CTI provides the interface between a processor or ETM and the CTM.

Cross Trigger Matrix (CTM)

In an ECT device, the CTM combines the trigger requests generated by CTIs and broadcasts them to all CTIs as channel triggers.

CTI

See Cross Trigger Interface (CTI).

CTM

See Cross Trigger Matrix (CTM).

Current Program Status Register (CPSR)

The register that holds the current operating processor status.

See Also Program Status Register and Saved Program Status Register.

Cycles Per Instruction (CPI)

A measure of the number of computer instructions that can be performed in one clock cycle, also called clocks per instruction. This value can be used to compare the performance of different processors that implement the same instruction set. The lower the value, the better the performance.

DAP

See Debug Access Port.

Data abort

An indication from a memory system to the processor of an attempt to access an illegal data memory location. An exception must be taken if the processor attempts to use the data that caused the abort.

See Also Abort, External abort, and Prefetch abort.

DBGTAP

See Debug Test Access Port.

Debug Access Port (DAP)

A block that acts as a master on a system bus and provides access to the bus from an external debugger.

Debug Test Access Port (DBGTAP)

A debug control and data interface based on the IEEE 1149.1 JTAG Test Access Port (TAP). The interface has four or five signals.

Debugger

A debugging system that includes a program, used to detect, locate, and correct software faults, together with custom hardware that supports software debugging.

Default NaN mode

In floating-point operation, a mode in which all operations that result in a NaN return the default NaN, regardless of the cause of the NaN result. This mode is compliant with the IEEE 754 standard but implies that all information contained in any input NaNs to an operation is lost.

See Also NaN.

Digital Signal Processing (DSP)

A variety of algorithms to process signals that have been sampled and converted to digital form. Saturated arithmetic is often used in such algorithms.

Dirty

A dirty cache line in a write-back cache is a line that has been modified while it is in the cache. Typically, a cache line is marked as dirty by setting the dirty bit to 1.

See Also Clean.

DNM

See Do Not Modify.

Do Not Modify (DNM)

A value that must not be altered by software. DNM fields read as unknown values, and must only be written with the value read from the same field on the same processor.

Double-precision value

In floating-point operation, consists of two 32-bit words that must appear consecutively in memory and are both word-aligned. The value is interpreted as a basic double-precision floating-point number according to the IEEE 754-1985 standard.

Doubleword

A 64-bit data item. Doublewords are normally at least word-aligned in ARM systems.

Doubleword-aligned

A data item having a memory address that is divisible by eight.

DSP

See Digital Signal Processing.

Embedded Trace Macrocell (ETM)

A hardware macrocell that, when connected to a processor, outputs trace information on a trace port. The ETM provides processor driven trace through a trace port compliant to the ATB protocol. An ETM always supports instruction trace, and might support data trace.

EmbeddedICE logic

An on-chip logic block that provides TAP-based debug support for an ARM processor. It is accessed through the DAP on the ARM processor.

EmbeddedICE-RT

Hardware provided by an ARM processor to aid debugging in real-time.

Endianness

The scheme that determines the order of successive bytes of a data word when it is stored in memory.

ETM

See Embedded Trace Macrocell.

Event

In an ARM trace macrocell, event has a particular meaning and these events can be simple or complex:

Simple

An observable condition that a trace macrocell can use to control aspects of a trace.

Complex

A boolean combination of simple events that a trace macrocell can use to control aspects of a trace.

Exception

A mechanism to handle a fault or error event. For example, exceptions handle external interrupts and undefined instructions.

Exception vector

A fixed address that contains the address of the first instruction of the corresponding exception handler.

External abort

An abort generated by the external memory system.

See Also Abort, Data abort and Prefetch abort.

Fast Context Switch Extension (FCSE)

An extension to the ARM architecture that modifies the behavior of the memory system. It enables multiple programs running on the processor to use identical address ranges, while ensuring that the addresses they present to the rest of the memory system differ.

From ARMv6, use of the FCSE is deprecated. The FCSE is optional in ARMv7, and obsolete from the ARMv7 Multiprocessing Extensions.

Fault

An abort generated by the memory system, for example by the Memory Management Unit (MMU).

FCSE

See Fast Context Switch Extension.

Flat address mapping

A system of organizing memory where the physical address for every access is equal to its virtual address.

Flush-to-zero mode

In floating-point operation, a special processing mode that optimizes the performance of some floating-point algorithms by replacing the denormalized operands and intermediate results with zeros, without significantly affecting the accuracy of their final results.

General-purpose register

See Core register.

Halfword

A 16-bit data item. Halfwords are normally halfword-aligned in ARM systems.

Halfword-aligned

A data item having a memory address that is divisible by 2.

Halting debug-mode

One of two mutually exclusive debug modes. In Halting debug-mode all processor execution halts when a breakpoint or watchpoint is encountered. You can examine and alter all processor state, coprocessor state, memory, input and output locations using the debug interface.

See Also Monitor debug-mode.

High registers

See Core register.

High vectors

Alternative locations for exception vectors. The high vector address range is near the top of the address space, rather than at the bottom.

Hint instruction

A hint instruction provides information that the hardware can take advantage of. A processor implementation can choose whether to implement hint instructions or not. If they are not implemented, they execute as NOP.

Host

A computer that provides data and other services to another computer. Especially, a computer providing debugging services to a target being debugged.

Immediate values

Values that are encoded directly in the instruction and used as numeric data when the instruction is executed. Many ARM and Thumb instructions can be used with an immediate argument.

Implementation-defined

Behavior that is not defined by the architecture, but is defined and documented by the implementation.

Implementation-specific

See Implementation-defined.

Index

See Cache index.

Instruction cycle count

The number of cycles for which an instruction occupies the Execute stage of the pipeline.

Internal scan chain

A series of registers connected together to form a path through a device, used during production testing to import test patterns into internal nodes of the device and export the resulting values.

Interrupt handler

See Exception handler.

Invalidate

Marking a cache line as being not valid, by clearing the valid bit to 0. This must be done whenever the line does not contain a valid cache entry. For example, after a cache flush all lines are invalid.

Jazelle state

In Jazelle state the processor executes Java bytecodes as part of a Java Virtual Machine (JVM).

See Also ARM state, Thumb state, and ThumbEE state.

JTAG Access Port (JTAG-AP)

An optional component of the DAP that provides debugger access to on-chip scan chains.

Load/store architecture

A processor architecture where data-processing operations only operate on register contents, not directly on memory contents.

Macrocell

A complex logic block with a defined interface and behavior. A typical VLSI system comprises several macrocells, such as a processor, an ETM, and a memory block integrated with application-specific logic.

Memory coherency

A memory is coherent if the value read by a data read or instruction fetch is the value that was most recently written to that location. Memory coherency is made difficult when the memory system includes multiple possible physical locations, such as main memory, a write buffer and one or more caches.

Memory Management Unit (MMU)

A hardware unit that provides detailed control of a memory system. Most of the control is provided by translation tables held in memory.

Memory Protection Unit (MPU)

A hardware unit that provides simple control of a limited number of protection regions in memory.

Miss

See Cache miss.

MMU

See Memory Management Unit.

Modified Virtual Address (MVA)

The address produced by the FCSE that is sent to the rest of the memory system to be used in place of the normal virtual address.

When the FCSE is absent or disabled, the MVA and the Virtual Address (VA) have the same value.

See Also Fast Context Switch Extension.

Monitor debug-mode

One of two mutually exclusive debug modes. In Monitor debug-mode the processor enables a software abort handler provided by the debug monitor or operating system debug task. When a breakpoint or watchpoint is encountered, system interrupts continue to be serviced while normal program execution is suspended.

See Also Halting debug-mode.

MPU

See Memory Protection Unit.

MVA

See Modified Virtual Address.

NaN

Not a number. In floating-point operation, NaNs are special floating-point values that can be used when neither a numeric value nor an infinity is appropriate. NaNs can be quiet NaNs that propagate through most floating-point operations, or signaling NaNs that cause Invalid Operation floating-point exceptions when used.

PA

See Physical Address.

Penalty

The number of cycles in which no useful Execute stage pipeline activity can occur because an instruction flow is different from that assumed or predicted.

Physical Address (PA)

The address that identifies a main memory location.

Power-on reset

See Cold reset.

Prefetch abort

An indication from a memory system to the processor that an instruction has been fetched from an illegal memory location. An exception must be taken if the processor attempts to execute the instruction. A Prefetch abort can be caused by the external or internal memory system as a result of attempting to access invalid instruction memory.

See Also Data abort, External abort and Abort.

Prefetching

The process of fetching instructions from memory before the instructions that precede them have finished executing. Prefetching an instruction does not mean that the instruction must be executed.

Privileged mode

Any processor mode other than User mode. Memory systems typically check memory accesses from privileged modes against supervisor access permissions rather than the more restrictive user access permissions. The use of some instructions is also restricted in privileged modes.

Programming Language Interface (PLI)

For Verilog simulators, an interface by which foreign code can be included in a simulation. Foreign code is code written in a different language.

Protection region

A memory region whose position, size, and other properties are defined by the Memory Protection Unit registers.

Read

Memory operations that have the semantics of a load. See the ARM Architecture Reference Manual for more information.

RealView ICE

ARM JTAG interface unit for debugging embedded processor cores that uses a DBGTAP or Serial Wire interface.

Remapping

Changing the address of physical memory or devices after the application has started executing. This might be done to permit RAM to replace ROM when the initialization has completed.

Reserved

Registers and instructions that are reserved are Unpredictable unless otherwise stated. Bit positions described as Reserved are UNK/SBZP.

Round to Nearest (RN) mode

In floating-point operation, the rounded result is the nearest representable number to the unrounded result. The tie case is rounded up if it would clear the least significant bit of the significand, making it even.

See Also Rounding mode, Rounding error.

Round towards Minus infinity (RM) mode

In floating-point operation, the rounded result is the nearest representable number that is less than or equal to the exact result. This rounding mode is used in interval arithmetic.

See Also Rounding mode, Rounding error.

Round towards Plus infinity (RP) mode

In floating-point operation, the rounded result is the nearest representable number that is greater than or equal to the exact result. This rounding mode is used in interval arithmetic.

See Also Rounding mode, Rounding error.

Round towards Zero (RZ) mode

In floating-point operation, results are rounded to the nearest representable number that is no greater in magnitude than the unrounded result. This rounding mode chops any bits to the right of the significand, always rounding down, and is used by the C, C++, and Java languages in integer conversions.

See Also Rounding mode, Rounding error.

Rounding error

Is defined to be the value of the rounded result of an arithmetic operation minus the exact result of the operation.

See Also Rounding mode.

Rounding mode

In floating-point operation, specifies how the exact result of a floating-point operation is rounded to a value that is representable in the destination format.

See Also Round to Nearest (RN) mode, Round towards Minus Infinity (RM) mode, Round towards Plus infinity (RP) mode, and Round towards Zero (RZ) mode.

Saved Program Status Register (SPSR)

The register that holds the CPSR of the task immediately before the exception occurred that caused the switch to the current mode. Each exception mode has its own SPSR.

SBO

See Should Be One.

SBZ

See Should Be Zero.

SBZP

See Should Be Zero or Preserved.

Set

See Cache set.

Short vector operation

A floating-point coprocessor operation involving more than one destination register and perhaps more than one source register in the generation of the result for each destination.

Should Be One (SBO)

Software must write as 1, or all 1s for bit fields. Writing any other value produces Unpredictable results.

Should Be Zero (SBZ)

Software must write as 0, or all 0s for bit fields. Writing any other value produces Unpredictable results.

Should Be Zero or Preserved (SBZP)

Software must write as 0, or all 0s for a bit field, if the value is being written without having previously been read, or if the register has not been initialized. If the register has previously been read, software must preserve the field value by writing back the value that was read from the same field on the same processor.

Signaling NaN

In floating-point operation, the floating-point coprocessor causes an Invalid Operation exception whenever any floating-point operation receives a signaling NaN as an operand. You can use signaling NaNs in debugging, to track down some uses of uninitialized variables.

SIMD

Single-Instruction, Multiple-Data operation.

SPSR

See Saved Program Status Register.

Subnormal value

In floating-point operation, a value in the range (-2Emin < x < 2Emin), except for plus or minus 0. In the IEEE 754 standard format for single-precision and double-precision operands, a subnormal value has a zero exponent and a nonzero fraction field. The IEEE 754 standard requires that the generation and manipulation of subnormal operands be performed with the same precision as normal operands.

Support code

In a floating-point implementation, system software that complements the hardware VFP implementation to provide compatibility with the IEEE 754 standard. The support code has a library of routines that perform supported functions, such as divide with unsupported inputs or inputs that might generate an exception, in addition to operations beyond the scope of the hardware. The support code has a set of exception handlers to process exceptional conditions in compliance with the IEEE 754 standard.

SVC

See Supervisor Call.

SWI

See Supervisor Call.

Synchronization primitive

An instruction that is used to ensure memory synchronization, for example LDREX or STREX. See the ARM Architecture Reference Manual for more information.

Tag bits

In a cache implementation, bits [31:(L+S)] of a virtual address, where L = log2 (cache line length) and S = log2 (number of cache sets). A cache hit occurs if the tag bits of the virtual address supplied by the processor match the tag bits associated with a valid line in the selected cache set.

See Also Cache terminology diagram on the last page of this glossary.

TCM

See Tightly Coupled Memory.

Thumb instruction

One or two halfwords that specify an operation for a processor in Thumb state to perform. Thumb instructions must be halfword-aligned.

See Also Thumb state, ThumbEE state.

Thumb state

In Thumb state the processor executes the Thumb instruction set.

ThumbEE state

In ThumbEE state the processor executes a variation of the Thumb instruction set specifically targeted for use with dynamic compilation techniques associated with an execution environment.

See Also ARM state, Jazelle state, Thumb state.

Tightly Coupled Memory (TCM)

An area of low latency memory that provides predictable instruction execution or data load timing in cases where deterministic performance is required. TCMs are suited to holding:

  • critical routines such as for interrupt handling

  • scratchpad data

  • data types whose locality is not suited to caching

  • critical data structures, such as interrupt stacks.

Tiny

In a floating-point operation, a nonzero result or value that is between the positive and negative minimum normal values for the destination precision.

TLB

See Translation Lookaside Buffer.

Trace hardware

A term for a device that contains an ARM trace macrocell.

Translation Lookaside Buffer (TLB)

A memory structure containing the results of translation table walks. TLBs help to reduce the average cost of memory accesses. Usually, there is a TLB for each memory interface of the processor implementation.

Trigger instruction

A floating-point instruction that causes a bounce when it is issued. A potentially exceptional instruction causes the floating-point coprocessor to enter the exceptional state. A subsequent instruction, unless it is an FMXR or FMRX instruction accessing the FPEXC, FPINST, or FPSID register, causes a bounce, starting exception processing. The trigger instruction might not be exceptional, and is not processed. It is retried at the return from the exception processing of the potentially exceptional instruction.

See Also Bounce, Potentially exceptional instruction, and Exceptional state.

Unaligned

An unaligned access is an access where the address of the access is not aligned to the size of an element of the access.

Undefined

Indicates an instruction that generates an Undefined Instruction exception. See the ARM Architecture Reference Manual for more information.

Unknown

An Unknown value does not contain valid data, and can vary from moment to moment, instruction to instruction, and implementation to implementation. An Unknown value must not be a security hole.

UNP

See Unpredictable.

Unpredictable

For a processor means the behavior cannot be relied on. Unpredictable behavior must not represent security holes. Unpredictable behavior must not halt or hang the processor, or any parts of the system.

Unpredictable

For an ARM trace macrocell, means that the behavior of the macrocell cannot be relied on. Such conditions have not been validated. When applied to the programming of an event resource, only the output of that event resource is Unpredictable. Unpredictable behavior can affect the behavior of the entire system, because the trace macrocell can cause the processor to enter debug state, and external outputs can be used for other purposes.

VA

See Virtual Address.

VFP

A coprocessor extension to the ARM architecture that provides floating-point arithmetic. For ARMv7, more accurately described as the Floating-Point Extension.

Victim

A cache line, selected to be discarded to make room for a replacement cache line that is required because of a cache miss. The way that the victim is selected for eviction is processor-specific. A victim is also known as a cast out.

Virtual Address (VA)

An address generated by an ARM processor. For a Protected Memory System Architecture (PMSA) implementation, the virtual address is identical to the physical address.

WA

See Write-Allocate cache.

Warm reset

Also known as a core reset. Initializes the majority of the processor excluding the debug controller and debug logic. This type of reset is useful if you are using the debugging features of a processor.

Watchpoint

A debug event triggered by an access to memory, specified in terms of the address of the location in memory being accessed.

See Also Breakpoint.

Way

See Cache way.

WB

See Write-Back cache.

Word

A 32-bit data item. Words are normally word-aligned in ARM systems.

Word-aligned

A data item having a memory address that is divisible by four.

Word-invariant

In a word-invariant system, the address of each byte of memory changes when switching between little-endian and big-endian operation, in such a way that the byte with address A in one endianness has address A EOR 3 in the other endianness. As a result, each aligned word of memory always consists of the same four bytes of memory in the same order, regardless of endianness. The change of endianness occurs because of the change to the byte addresses, not because the bytes are rearranged.

The ARM architecture supports word-invariant systems in ARMv3 and later versions. When word-invariant support is selected, the behavior of load or store instructions with unaligned addresses is instruction-specific, and is in general not the expected behavior for an unaligned access. ARM strongly recommends that word-invariant systems use the endianness that produces the required byte addresses at all times, apart possibly from very early in their reset handlers before they have set up the endianness, and that this early part of the reset handler uses only aligned word memory accesses.

See Also Byte-invariant.

Write

Operations that have the semantics of a store. See the ARM Architecture Reference Manual for more information.

Write buffer

A block of high-speed memory implemented to optimize stores to main memory.

Write interleave capability

The number of data-active write transactions for which the interface can transmit data. This is counted from the earliest transaction.

Write interleave depth

The number of data-active write transactions for which the interface can receive data.

Write-Allocate cache

A cache where a cache miss on storing data causes a cache line to be allocated and main memory contents to be read into it, followed by writing the stored data into the cache line.

Write-Back cache

A cache where, when a cache hit occurs on a store access, the data is only written to the cache. Data in the cache can therefore be more up-to-date than data in main memory.

Any such data is written back to main memory when the cache line is cleaned or re-allocated. Also called copy-back cache.

Write-Through cache

A cache in which, when a cache hit occurs on a store access, the data is written both to the cache and to main memory. This is normally done using a write buffer, to avoid slowing down the processor.

WT

See Write-Through cache.

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