A.5.3. AXI slave port

Table A.7 shows the AXI slave port signals for the L2 interface. With the exception of the ACLKENSm, all signals are only sampled or driven on CLKIN edges when ACLKENSm is asserted, see AMBA interface clocking for more information.

Table A.7. AXI slave port signals for the L2 interface

SignalDirectionDescription
ACLKENSmInputClock enable for the AXI slave port.
Write Address Channel
 AWADDRSm[31:0]InputTransfer start address.
 AWBURSTSm[1:0]InputWrite burst type.
 AWCACHESm[3:0]InputWrite address outer attribute information.
 AWCSELSm[3:0]InputMemory type select data cache, instruction cache, BTCM or ATCM, one hot.[a]
 AWIDSm[7:0]InputThe identification tag for the write address group of signals.
 AWLENSm[3:0]InputWrite transfer burst length.
 AWLOCKSm[1:0]InputLock signal.
 AWPROTSm[2:0]InputProtection information, privileged/normal access.
 AWREADYSmOutputAddress ready. The slave uses this signal to indicate that it can accept the address.
 AWSIZESm[2:0]InputIndicates the size of the transfer.
 AWVALIDSmInputIndicates address and control are valid.
Write Data Channel
 WDATASm[63:0]InputWrite data.
 WIDSm[7:0]InputThe identification tag for the write group of signals.
 WLASTSmInputIndicates the last data transfer of a burst.
 WREADYSmOutputIndicates that the slave is ready to accept write data.
 WSTRBSm[7:0]InputWrite strobes used to indicate which byte lanes must be updated.
 WVALIDSmInputIndicates address and control are valid.
Write Response Channel
 BIDSm[7:0]OutputThe identification tag for the write response signal.
 BREADYSmInputIndicates that the CPU is ready to accept write response.
 BRESPSm[1:0]Output

Write response.

 BVALIDSmOutputIndicates that a valid write response is available.
Read Address Channel
 ARADDRSm[31:0]InputInstruction fetch burst start address.
 ARBURSTSm[1:0]InputBurst type.
 ARCACHESm[3:0]InputRead address outer attribute information.
 ARIDSm[7:0]InputIdentification tag for the read address group of signals.
 ARLENSm[3:0]InputInstruction fetch burst length.
 ARLOCKSm[1:0]InputLock signal.
 ARPROTSm[2:0]InputProtection information, privileged/normal access.
 ARREADYSmOutputAddress ready. The slave uses this signal to indicate that it can accept the address.
 ARSIZESm[2:0]InputIndicates the size of the transfer.
 ARCSELSm[3:0]InputMemory type select {data cache, instruction cache, BTCM or ATCM}, one hot.[a]
 ARVALIDSmInputIndicates address and control are valid.
Read Data Channel
 RDATASm[63:0]OutputRead data.
 RIDSm[7:0]OutputThe identification tag for the read data group of signals.
 RLASTSmOutputIndicates the last transfer in a read burst.
 RREADYSmInputRead ready signal indicating that the bus master can accept read data and response information.
 RRESPSm[1:0]OutputRead response.
 RVALIDSmOutputIndicates address and control are valid.

[a] This is an AXI extension signal.


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