9.3.5. Non-cacheable reads

Load instructions accessing Non-cacheable Normal memory generate AXI bursts that are not necessarily the same size or length as the instruction implies. In addition, if the data to be read is contained in the store buffer, the instruction might not generate an AXI read transaction at all.

The tables in this section give examples of the types of AXI transaction that might result from various load instructions, accessing various addresses in Non-cacheable Normal memory. They are provided as examples only, and are not an exhaustive description of the AXI transactions. Depending on the state of the processor, and the timing of the accesses, the actual bursts generated might have a different size and length to the examples shown, even for the same instruction.

Table 9.13 shows possible values of ARADDRMm, ARBURSTMm, ARSIZEMm, and ARLENMm for an LDRH from bytes 0-7 in Non-cacheable Normal memory.

Table 9.13. LDRH from Non-cacheable Normal memory

Address[2:0]ARADDRMmARBURSTMmARSIZEMmARLENMm
0x0 (byte 0)0x00Incr16-bit1 data transfer
0x1 (byte 1)0x00Incr32-bit1 data transfer
0x2 (byte 2)0x00Incr64-bit1 data transfer
0x3 (byte 3)0x03Incr32-bit2 data transfers
0x4 (byte 4)0x04Incr16-bit1 data transfer
0x5 (byte 5)0x04Incr32-bit1 data transfer
0x6 (byte 6)0x06Incr16-bit1 data transfer
0x7 (byte 7)0x07Incr32-bit2 data transfers

Table 9.14 shows possible values of ARADDRMm, ARBURSTMm, ARSIZEMm, and ARLENMm for a Non-cacheable LDR or an LDM that transfers one register, an LDM1.

Table 9.14. LDR or LDM1 from Non-cacheable Normal memory

Address[2:0]ARADDRMmARBURSTMmARSIZEMmARLENMm
0x0 (byte 0) (word 0)0x00Incr32-bit1 data transfer
0x1 (byte 1)0x01Incr64-bit1 data transfer
0x2 (byte 2)0x00Incr64-bit1 data transfer
0x3 (byte 3)0x00Incr64-bit2 data transfers
0x4 (byte 4) (word 1)0x04Incr32-bit1 data transfer
0x5 (byte 5)0x05Incr32-bit2 data transfers
0x6 (byte 6)0x06Incr16-bit1 data transfer
0x08Incr16-bit1 data transfer
0x7 (byte 7)0x04Incr32-bit2 data transfers

Table 9.15 show possible values of ARADDRMm, ARBURSTMm, ARSIZEMm, and ARLENMm for a Non-cacheable LDM that transfers five registers (an LDM5).

Table 9.15. LDM5, Non-cacheable Normal memory or cache disabled

Address[4:0]ARADDRMmARBURSTMmARSIZEMmARLENMm
0x00 (word 0)0x00Incr64-bit3 data transfers
0x04 (word 1)0x04Incr64-bit3 data transfers
0x08 (word 2)0x08Incr64-bit3 data transfers
0x0C (word 3)0x0CIncr64-bit3 data transfers
0x10 (word 4)0x10Incr64-bit2 data transfers
0x00Incr32-bit1 data transfer
0x14 (word 5)0x14Incr64-bit2 data transfers
0x00Incr64-bit1 data transfer
0x18 (word 6)0x18Incr64-bit1 data transfer
0x00Incr64-bit2 data transfers
0x1C (word 7)0x1CIncr32-bit1 data transfer
0x00Incr64-bit2 data transfers

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