9.3.2. Strongly Ordered and Device transactions

A load or store instruction to or from Strongly Ordered or Device memory always generates AXI transactions of the same size as implied by the instruction. All accesses using LDM, STM, LDRD, or STRD instructions to Strongly Ordered or Device memory occur as 32-bit transfers.

LDRB

Table 9.3 shows the values of ARADDRMm, ARBURSTMm, ARSIZEMm, and ARLENMm for a Non-cacheable LDRB from bytes 0-7 in Strongly Ordered or Device memory.

Table 9.3. Non-cacheable LDRB

Address[2:0]ARADDRMmARBURSTMmARSIZEMmARLENMm
0x0 (byte 0)0x00Incr8-bit1 data transfer
0x1 (byte 1)0x01Incr8-bit1 data transfer
0x2 (byte 2)0x02Incr8-bit1 data transfer
0x3 (byte 3)0x03Incr8-bit1 data transfer
0x4 (byte 4)0x04Incr8-bit1 data transfer
0x5 (byte 5)0x05Incr8-bit1 data transfer
0x6 (byte 6)0x06Incr8-bit1 data transfer
0x7 (byte 7)0x07Incr8-bit1 data transfer

LDRH

Table 9.4 shows the values of ARADDRMm, ARBURSTMm, ARSIZEMm, and ARLENMm for a Non-cacheable LDRH from halfwords 0-3 in Strongly Ordered or Device memory.

Table 9.4. LDRH from Strongly Ordered or Device memory

Address[2:0]ARADDRMmARBURSTMmARSIZEMmARLENMm
0x0 (halfword 0)0x00Incr16-bit1 data transfer
0x2 (halfword 1)0x02Incr16-bit1 data transfer
0x4 (halfword 2)0x04Incr16-bit1 data transfer
0x6 (halfword 3)0x06Incr16-bit1 data transfer

Note

A load of a halfword from Strongly Ordered or Device memory addresses 0x1, 0x3, 0x5, or 0x7 generates an alignment fault.

LDR or LDM that transfers one register

Table 9.5 shows the values of ARADDRMm, ARBURSTMm, ARSIZEMm, and ARLENMm for a Non-cacheable LDR or an LDM that transfers one register, (an LDM1) in Strongly Ordered or Device memory.

Table 9.5. LDR or LDM1 from Strongly Ordered or Device memory

Address[2:0]ARADDRMmARBURSTMmARSIZEMmARLENMm
0x0 (word 0)0x00Incr32-bit1 data transfer
0x4 (word 1)0x04Incr32-bit1 data transfer

Note

A load of a word from Strongly Ordered or Device memory addresses 0x1, 0x2, 0x3, 0x5, 0x6, or 0x7 generates an alignment fault.

LDM that transfers five registers

Table 9.6 shows the values of ARADDRMm, ARBURSTMm, ARSIZEMm, and ARLENMm for a Non-cacheable LDM that transfers five registers (an LDM5) in Strongly Ordered or Device memory.

Table 9.6. LDM5, Strongly Ordered or Device memory

Address[3:0]ARADDRMmARBURSTMmARSIZEMmARLENMm
0x0 (word 0)0x00Incr32-bit5 data transfers
0x4 (word 1)0x04Incr32-bit5 data transfers
0x8 (word 2)0x08Incr32-bit5 data transfers
0xC (word 3)0x0CIncr32-bit5 data transfers

Note

A load-multiple from address 0x1, 0x2, 0x3, 0x5, 0x6, 0x7, 0x9, 0xA, 0xB, 0xD, 0xE, or 0xF generates an alignment fault.

STRB

Table 9.7 shows the values of AWADDRMm, AWBURSTMm, AWSIZEMm, and AWLENMm for an STRB to Strongly Ordered or Device memory over the AXI master port.

Table 9.7. STRB to Strongly Ordered or Device memory

Address[2:0]AWADDRMmAWBURSTMmAWSIZEMmAWLENMmWSTRBMm
0x0 (byte 0)0x00Incr8-bit1 data transferb00000001
0x1 (byte 1)0x01Incr8-bit1 data transferb00000010
0x2 (byte 2)0x02Incr8-bit1 data transferb00000100
0x3 (byte 3)0x03Incr8-bit1 data transferb00001000
0x4 (byte 4)0x04Incr8-bit1 data transferb00010000
0x5 (byte 5)0x05Incr8-bit1 data transferb00100000
0x6 (byte 6)0x06Incr8-bit1 data transferb01000000
0x7 (byte 7)0x07Incr8-bit1 data transferb10000000

STRH

Table 9.8 shows the values of AWADDRMm, AWBURSTMm, AWSIZEMm, and AWLENMm for an STRH over the AXI master port to Strongly Ordered or Device memory.

Table 9.8. STRH to Strongly Ordered or Device memory

Address[2:0]AWADDRMmAWBURSTMmAWSIZEMmAWLENMmWSTRBMm
0x0 (halfword 0)0x00Incr16-bit1 data transferb00000011
0x2 (halfword 1)0x02Incr16-bit1 data transferb00001100
0x4 (halfword 2)0x04Incr16-bit1 data transferb00110000
0x6 (halfword 3)0x06Incr16-bit1 data transferb11000000

Note

A store of a halfword to Strongly Ordered or Device memory addresses 0x1, 0x3, 0x5, or 0x7 generates an alignment fault.

STR or STM of one register

Table 9.9 shows the values of AWADDRMm, AWBURSTMm, AWSIZEMm, and AWLENMm for an STR or an STM that transfers one register (an STM1) over the AXI master port to Strongly Ordered or Device memory.

Table 9.9. STR or STM1 to Strongly Ordered or Device memory

Address[2:0]AWADDRMmAWBURSTMmAWSIZEMmAWLENMmWSTRBMm
0x0 (word0)0x00Incr32-bit1 data transferb00001111
0x4 (word 1)0x04Incr32-bit1 data transferb11110000

Note

A store of a word to Strongly Ordered or Device memory addresses 0x1, 0x2, 0x3, 0x5, 0x6, or 0x7 generates an alignment fault.

STM of seven registers

Table 9.10 shows the values of AWADDRMm, AWBURSTMm, AWSIZEMm, and AWLENMm for an STM that writes seven registers (an STM7) over the AXI master port to Strongly Ordered or Device memory.

Table 9.10. STM7 to Strongly Ordered or Device memory to word 0 or 1

Address[4:0]AWADDRMmAWBURSTMmAWSIZEMmAWLENMm

First WSTRBMm

0x00 (word 0)0x00Incr32-bit7 data transfersb00001111
0x04 (word 1)0x04Incr32-bit7 data transfersb11110000

Note

A store-multiple to address 0x1, 0x2, 0x3, 0x5, 0x6, or 0x7 generates an alignment fault.

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